| • | Capable of running all existing 16450 software. |
| • | Pin for pin compatible with the existing 16450 except for CSOUT (24) and NC (29). The former CSOUT and NC pins are TXRDY# and RXRDY#, respectively. |
| • | After reset, all registers are identical to the 16450 register set. |
| • | In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO's to reduce the number of interrrupts presented to the CPU. |
| • | Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data. |
| • | Holding and shift registers in the 16450 Mode eliminate the need for precise synchronization between the CPU and serial data. |
| • | Independently controlled transmit, receive, line status, and data set interrupts. |
| • | Programmable baud generator divides any input clock by 1 to (216 - 1) and generates the 16 × clock. |
| • | Independent receiver clock input. |
| • | MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD). |
| • | Fully programmable serial-interface characteristics:
|
| • | 5-, 6-, 7-, or 8-bit characters |
| • | Even, odd, or no-parity bit generation and detection |
| • | 1-, 1½-, or 2-stop bit generation |
| • | Baud generation (DC to 1.5M baud). |
| • | False start bit detection. |
| • | Complete status reporting capabilities. |
| • | TRI-STATE® TTL drive for the data and control buses. |
| • | Line break generation and detection. |
| • | Internal diagnostic capabilities:
|
| • | Loopback controls for communications link fault isolation |
| • | Break, parity, overrun, framing error simulation. |
| • | Full prioritized interrupt system controls. |
RoHS Compliance Information
