LP2996 - DDR Termination Regulator
Datasheet Packaging Samples & Pricing Eval. Boards Reliability Application Notes Knowledge Base

Features
•Source and sink current
•Low output voltage offset
•No external resistors required
•Linear topology
•Suspend to Ram (STR) functionality
•Low external component count
•Thermal Shutdown
•Available in SO-8, PSOP-8 or LLP-16 packages

General Description

The LP2996 linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. More...


Applications

•DDR-I and DDR-II Termination Voltage
•SSTL-2 and SSTL-3 Termination
•HSTL Termination
  Typical Application
click for larger image


ParametersValues
Input Min Voltage 1.5 Volt
Input Max Voltage 5.5 Volt
Output Current 1500 mA
Standards DDR, DDR-II
External Components 3
Independent Power/Analog Rails No
On/Off Pin Yes
Reference Output 1.25 Volt
Thermal Protection Yes
Special Features Suspend to RAM shutdown
Error Flag No
Quiescent Current 0.32 mA
RegType LDO
Temperature Min 0 deg C
Temperature Max 125 deg C


Typical Performance

click for larger image


  Also Recommended
LM2744▲Switching Termination Regulator
LP2997▲DDR-II Linear Termination Regulator
LP2998▲Industrial Temp Range (-40C To 125C) DDR-I And DDR-II Linear Termination Regulator
Additional Resources
Online Seminars Application Notes


Block Diagram

click for larger image



Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
LP2996 DDR Termination Regulator 371
Kbytes		 28-Apr-09 Download
LP2996 DDR Termination Regulator (Japanese)
 658 Kbytes   Download

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Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders		Budgetary PricingStd
Pack
Size		Package
Marking
Format
TypePinsSpec.MSL
Rating		Peak
Reflow		RoHS
Report		CAD
Symbols		WeeksQtyQty$US each
LP2996LQEVALDDR Termination RegulatorFull productionN/A
 
Buy Now 		1+$10.501-
8 weeksN/A
LP2996MREVALDDR Termination RegulatorFull productionN/A
 
Buy Now 		1+$10.501-
8 weeksN/A
LP2996LQLLP16NOPB
STD		3
1		260
235		RoHS Download Full productionN/A
Samples
Buy Now 		1K+$0.62reel
of
1000		NS
UZXYTT
L00006B
8 weeks15000
LP2996LQXLLP16NOPB3260RoHS Download Full productionN/A
 
Buy Now 		1K+$0.62reel
of
4500		NS
UZXYTT
L00006B
8 weeks7500
LP2996MSOIC NARROW8NOPB1260RoHS Download Full productionN/A
Samples
Buy Now 		1K+$0.62rail
of
95		NSZXTT
2996M
8 weeks1000
LP2996MXSOIC NARROW8NOPB1260RoHS Download Full productionN/A
 
Buy Now 		1K+$0.62reel
of
2500		NSZXTT
2996M
8 weeks7500
LP2996MRPSOP8NOPB
STD		3
3		260
260		RoHS Download Full productionN/A
Samples
Buy Now 		1K+$0.62rail
of
95		NSXYTT
LP2996
8 weeks2000
LP2996MRXPSOP8NOPB
STD		3
3		260
260		RoHS Download Full productionN/A
 
Buy Now 		1K+$0.62reel
of
2500		NSXYTT
LP2996
6 weeks5000

General Description

The LP2996 linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996 is an active low shutdown ( ^SD) pin that provides Suspend To RAM (STR) functionality. When ^SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

Reliability Metrics

Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
LP2996LQCS065238968520440200011249079519
LP2996LQXCS065238968520440200011249079519
LP2996MCS065238968520440200011249079519
LP2996MRCS065238968520440200011249079519
LP2996MRXCS065238968520440200011249079519
LP2996MXCS065238968520440200011249079519

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


Application Notes

TitleSize in Kbytes Date Click link below to Download
AN-1268: Application Note 1268 LP2996 Evaluation Board 67
Kbytes		 5-Dec-02 Download

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More Application Notes

TitleSize in Kbytes Date Click link below to Download
AN-1241: Application Note 1241 LP2995 Evaluation Board 373
Kbytes		 25-Sep-02 Download
AN-1813: Application Note 1813 LP2998 Evaluation Board 975
Kbytes		 10-Mar-08 Download
AN-1254: Application Note 1254 DDR-SDRAM Termination Simplified Using a Linear Regulator 49
Kbytes		 1-Oct-02 Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 8-Nov-2009]