Features 30 fs additive jitter (100 Hz to 20 MHz) Dual clock inputs Programmable output channels (0 to 1600 MHz) External synchronization Pin compatible family of clocking devices 3.15 to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) Device LVDS Outputs LVPECL Outputs LMK01000 3 5 LMK01010 8 0 LMK01020 0 8 Description The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-in-class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners. The LMK01000 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains. Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*).

Also Recommended LMK01000 1.6 GHz Low-Noise Clock Distributor (LVPECL/LVDS Outputs) LMK02000 Clock Jitter Cleaner With External VCXO (LVPECL/LVDS Outputs) LMK02002 Clock Jitter Cleaner With External VCXO (LVPECL Outputs) LMK01020▲ 1.6 GHz Low-Noise Clock Distributor (LVPECL Outputs) LMK03002C▲ Clock Jitter Cleaner With Integrated 1.7 GHz VCO (LVPECL Outputs) System Diagram MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image System Diagram	Block Diagram *click for larger image Functional Block Diagram
Typical Performance *click for larger image LVPECL Output Noise Floor

Datasheet

Title		Size	Date	Other Language
	LMK01000 Family LMK01000 Family 1.6 GHz High Performance Clock Buffer, Divider, and Distributor	522 Kbytes	15-Oct-09

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Design Tools

Title	Size	Date
More design resources for the LMK clock conditoners
Clock Design Tool and Other Software for LMK Clock Conditioners