Features • Power Savings • Self-refreshed Partial Display Mode • Provides timing signal for on-glass charge-sharing circuit • Standard Command Set • Registers initialized from on-chip EEPROM • Command-triggered profiles can change register settings for modes/gamma settings • Eliminates frequent host SW changes to update register settings • 8 user-defined display configurations • Programmable Settings • Display resolution and glass signal timing • Video interface timing auto-learning circuit • VID_XFR output reduces tearing in partial mode • Gamma curves and VCOM adjustment • Advanced Display Features (evaluation only) • Configurable Partial Mode Window size, location and color depth • Self-refreshed partial display mode supports 1–bit and 3–bit depths • OSD function with Partial RAM data in video mode • Alpha blending, including transparent mode • Video 2x upscale with programmable border • Partial Window 2x upscale with border color • Interfaces • Serial Interface (LoSSI) for commands, register access and partial memory access • 24–bit RGB Video interface • MPL1 high-speed serial interface Description The FPD95120 is a 320–channel LTPS/CGS driver with Partial Display Memory, a 24–bit RGB video interface and enhanced display quality. It provides 320 output source drivers with a 1:3 glass multiplex ratio. It includes a 230,400–bit memory for partial display modes, a timing controller with glass interface level-shifters, AC and DC VCOM drive schemes and glass power supply circuits. The output format can be configured to drive arbitrary display resolutions up to 320RGB columns. Advanced processing features enable up-scaling of incoming video to accommodate legacy graphics. There is also an upscale function for the Partial Display window to enable larger window sizes. The on-chip Partial Display Memory is configurable in window size, location and color depth. This memory can support partial display windows such as 240x320 in 3–bit mode and 320x720 in 1–bit color mode. The partial display memory can be used to self-refresh a region of the display in a reduced power state or as an overlay for OSD and alpha-blending features. The FPD95120 also includes independent RGB gamma curve adjustments as well as user-definable color palettes for 1–bit and 3–bit Partial Display modes. A low-speed serial interface (LoSSI) is provided to control display operating modes and provide access to the Partial Display Memory. This interface can support both 8–bit and 9–bit protocols. A standard command set is supported to set display modes and operating parameters. Customized register profiles associated with each command are loaded from an on-chip EEPROM. Registers can also be directly accessed by using the Register Access Mode.

Also Recommended FPD95320▲ Improved Performance MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image

Datasheet

Title		Size	Date	Other Language
	FPD95120 320-Channel LTPS/CGS Driver with MPL1 Interface	218 Kbytes	10-Jun-07

Featured Application Notes

Title		Size	Date	Other Language
	AN-1235: Application Note 1235 Using Smart Charge Sharing to Reduce Power and Boost Column Driver Performance	73 Kbytes	14-May-04
	AN-1237: Application Note 1237 RSDS™ Flat Panel Display Design Guidelines Part 2	141 Kbytes	14-May-03

More Application Notes

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	AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	中文

Design Tools

Title	Size	Date
Article - Optimizing Power Consumption in the Mobile Multimedia Delivery Chain - Part One
Article - Optimizing Power Consumption in the Mobile Multimedia Delivery Chain - Part Two

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
FPD95120DSCG	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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