Features Applications PHYTER® is a registered trademark of National Semiconductor Corporation. • Ultra low power consumption typically 1.1 watt • Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications • Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12 • 3.3V or 2.5V MAC interfaces: • IEEE 802.3u MII • IEEE 802.3z GMII • RGMII version 1.3 • User programmable GMII pin ordering • IEEE 802.3u Auto-Negotiation and Parallel Detection • Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices • Speed Fallback mode to achieve quality link • Cable length estimator • LED support for activity, full / half duplex, link1000, link100 and link10, user programmable (manual on/off), or reduced LED mode • Supports 25 MHz operation with crystal or oscillator. • Requires only two power supplies, 1.8V (core and analog) and 2.5V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage • User programable interrupt • Supports Auto-MDIX at 10, 100 and 1000 Mb/s • Supports JTAG (IEEE1149.1) • 128-pin PQFP package (14mm x 20mm) Description The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductors South Portland, Maine facility. The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII). The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure. Applications The DP83865 fits applications in: • 10/100/1000 Mb/s capable node cards • Switches with 10/100/1000 Mb/s capable ports • High speed uplink ports (backbone)

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Datasheet

Title		Size	Date	Other Language
	DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer	591 Kbytes	11-Dec-07

Featured Application Notes

Title		Size	Date	Other Language
	AN-1263: Application Note 1263 DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer Design Guide	250 Kbytes	14-Oct-09
	AN-1301: Application Note 1301 Dual Foot Print Layout Notes for DP83865 Gig PHYTER V and DP83847 DS PHYTER II	48 Kbytes	24-Oct-03	中文
	AN-1408: Application Note 1408 Designing Power Over Ethernet Using LM5070 and DP83865	1072 Kbytes	10-Jan-06	中文
	AN-1329: Application Note 1329 DP83865 and DP83864 Gigabit Physical Layer Device Trouble Shooting Guide	274 Kbytes	26-May-04
	AN-1511: Application Note 1511 Cable Discharge Event	546 Kbytes	6-Jul-06	日本語 中文

More Application Notes

Title		Size	Date	Other Language
	AN-1301: Application Note 1301 Dual Foot Print Layout Notes for DP83865 Gig PHYTER V and DP83847 DS PHYTER II	48 Kbytes	24-Oct-03	中文
	AN-1408: Application Note 1408 Designing Power Over Ethernet Using LM5070 and DP83865	1072 Kbytes	10-Jan-06	中文
	AN-1263: Application Note 1263 DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer Design Guide	250 Kbytes	14-Oct-09
	AN-1511: Application Note 1511 Cable Discharge Event	546 Kbytes	6-Jul-06	日本語 中文

Design Tools

Title	Size	Date
DP83865 Reference Design
DP83865 Reference Design Resources

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DP83865DVH	CMOS9	1	7327	137	0	1103000	4	312979261

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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