* BEGIN MODEL LMV841
* Rev. A October-2007
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Corporation.
* Models developed and under copyright by:
* National Semiconductor, Corporation.  
*/////////////////////////////////////////////////////////////////////
* Legal Notice:  
* The model may be copied, and distributed without any modifications;
* however, reselling or licensing the material is illegal.
* We reserve the right to make changes to the model without prior notice. 
* Pspice Models are provided "AS IS, WITH NO WARRANTY OF ANY KIND" 
*////////////////////////////////////////////////////////////////////
*MODEL KEY FEATURES INCLUDE:
* OUTPUT SWING, OPEN LOOP GAIN AND PHASE, SLEW RATE, 
* COMMON MODE REJECTION vs FREQUENCY, POWER SUPPLY REJECTION vs FREQUENCY,
* INPUT VOLTAGE NOISE WITH 1/F, OUTPUT SATURATION VOLTAGE,
* INPUT CAPACITANCE, INPUT BIAS CURRENT, INPUT COMMON MODE RANGE, 
* INPUT OFFSET VOLTAGE, QUIESCENT SUPPLY CURRENT.
*/////////////////////////////////////////////////////////////////////
*MODEL TEMP RANGE IS +25 DEG C (ROOM TEMP ONLY).
* Vsupply = +5V
* DEVICE PINOUT ORDER  +IN -IN +V -V OUT
* DEVICE PIN NUMBER     1   3   5  2  4 
* ///////////////////////////////////////////////////////////////////
* Node Assignments
*                   noninverting input
*                      | inverting input
*                      |   |  positive supply
*                      |   |    |  negative supply
*                      |   |    |   |   output
*                      |   |    |   |   |
*                      |   |    |   |   |
.SUBCKT LMV841         1   2    99  50  45
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=1.59E-03
M2   6  2  8  8 PIX L=1E-6 W=1.59E-03
M3  14  7 18 18 NIX L=1E-6 W=1.59E-03
M4  16  2 18 18 NIX L=1E-6 W=1.59E-03
RD1  4 50 4.00E+03
RD2  6 50 4.00E+03
RD3 99 14 4.00E+03
RD4 99 16 4.00E+03
C1   4  6 1.70E-12
C2  14 16 1.70E-12
I1  99  8 1.00E-04
I2  18 50 1.00E-04
V1  99  9 1.121E+00
V2  19 50 1.121E+00
D1   8  9 DX
D2  19 18 DX
EOS  7  1 POLY(4) (73,98) (22,98) (81,98) (83,98) 5.00E-04 1 1 1 1
IOS  1  2 2.00E-14
*
*CMRR Network
*
E1  72 98 POLY(2) (1,98) (2,98) 0 2.81E-01 2.81E-01
R10 72 73 1.59E+02
R20 73 98 1.59E-02
C10 72 73 1.00E-06
*
* PSRR Network
*
EPSY 21 98 POLY(1) (99,50) -2.81E-02 5.62E-03
RPS1 21 22 1.59E+00
RPS2 22 98 1.59E-02
CPS1 21 22 1.00E-06
*
* VOLTAGE NOISE REFERENCE OF 12nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 1.97E+01
RN2 81 98 1
*
* FLICKER NOISE CORNER = 5000 Hz
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.6551
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) -6.618E-03 1.50E-05
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(2) (4,6) (14,16) 0 2.10E-03 2.10E-03
R1 30 98 1.00E+06
RZ 45 31 7.145E+01
CF 30 31 6.727E-10
V3 32 30 8.77E-01
V4 30 33 2.00E+00
D3 32 97 DX
D4 51 33 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=4.44E-04
M6  45 47 50 50 NOX L=1E-6 W=2.00E-04
EG1 99 46 POLY(1) (98,30) 2.124E+00 1
EG2 47 50 POLY(1) (30,98) 3.005E+00 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.5,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=1.00E-05,VTO=0.5,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=0.1)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=2E-9)
*
*
.ENDS 
* ENDS MODEL LMV841