Wireless How can I create a BOM (Bill of Materials) for a regulator, PLL, or amplifier application? Using the wireless WEBENCH online design tools, you can create a regulator, PLL, or amplifier application. The design process includes developing a bill of materials (BOM) and initial evaluation of circuit performance through simulation. How can I gain access to resources for Simply Blue and LMX9838-based systems? Resources for developers of Simply Blue and LMX9838-based systems are available from the LMX9838 Bluetooth Serial Port Module page, here: http://www.national.com/analog/wireless/lmx9838. This information had previously been password-protected on the "Simply Blue Developers Page", but is now publicly accessible. Relevant Part: LMX9838,;LM9838 Can I use several links in transparent mode on the LMX9838? No, the device can switch to transparent mode if one link only is active. If several Bluetooth links are created, the LMX9838 can be used in command mode only. Relevant Part: LMX9838 How can I reach high data reliability over my Bluetooth link? The LMX9838 acts as pure gateway between the UART and the Bluetooth interface. It routes the information from either interface to the other, without modifying the content or adding additional consistency checks into it. For high reliability of the data transmission, it is recommended to implement checksum or flow control information into the transmitted data by the host application. Relevant Part: LMX9838 How does the LMX9838 send a specific packet type (DH1, DH5, DM1, ...)? In a normal operation mode, the packet type is chosen automatically by the baseband depending on the RFCOMM status and availability and the amount of bytes sent. The packet type selection is completely transparent to the user and can not be done manually. In test mode, the RF_TEST_MODE command allows the user to select manually the packet type and other parameters necessary for the specific test. Relevant Part: LMX9838 I can see incoming bytes when resetting the LMX9838, but it does not accept any commands. Please check if the actual baudrate and UART settings correspond to the settings made on the OP pins and in NVS. It needs to be made sure, that OP3, 4 and 5 have the correct values at startup, using either 1k pull-up resistors or pull to GND. Relevant Part: LMX9838 I cannot create a link between the LMX9838 and a remote device. Please verify the following points: The local port to be used is opened (Use command SET_PORTS_TO_OPEN) The Pin code is the same on both devices. The remote device is connectable and Bluetooth is turned ON. Some devices do not accept the role master switch. Try disabling the Force Master mode (Use command FORCE_MASTER). Relevant Part: LMX9838 The actual baudrate of the LMX9838 does not correspond to the selected value. Please make sure that the OP pin pull-up resistors are not more than 1kOhm in value. In case the configuration is set to "Read from NVS", please make sure the correct value is stored in the device. Since the NVS setting is ignored if a fixed rate is set by the OP pins, select one of those defined baudrates, set the NVS value to the desired value and switch back to "Read from NVS". After Reset it should come up with the correct baudrate. Relevant Part: LMX9838 When sending a command to the LMX9838, I do not get the confirm event including the command status. Try the following steps: Try to set the event filter to not filter any message (setting 00). Make sure that the command set exists. Also check Start delimiter, header, opcode, checksum, payload size, and end delimiter. Check the UART interface: Baudrate Parity and stop bits Relevant Part: LMX9838 How is a dual PLL configured if only one side of it is to be used? Power should be applied to both sides of the PLL, and the side that is not used should be programmed as "power down". The inputs and outputs of the unused side should be left open Relevant Part: PLL Is there an easy way to program a COP microcontroller to control a PLL without having to learn COP8 programming language? Yes, see application note AN-1098 for an easy technique. This application note describes the hardware and software required for loading Single or Dual Frequency Synthesizers for RF Communications with National Semiconductor’s COP8 family of microcontrollers. The specific example is for a LMX2320 PLLatinum Frequency Synthesizer and a COP8SAA7 Microcontroller. COP8SAx7 is an excellent choice for a low cost, single chip solution for configuring all parameters necessary for the frequency synthesizer. WEBENCH online design tools are also available for National''s PLLs and the COP8SAA7. Relevant Part: PLL Can a PLL be used to control a VCO that requires a higher input voltage than the charge pump output voltage of the PLL? Yes. An op-amp can be used to boost the charge pump voltage by creating an active filter. Information on this is available at wireless.national.com. At this website, the EasyPLL online design program can be used to both design and simulate active filters with op-amps. Phase noise simulations include op-amp noise. Also, at wireless.national.com is a book called "PLL Performance, Simulation, and Design" by Dean Bannerjee, which has a few chapters devoted to active filter design. Relevant Part: PLL Can a PLL counter be programed with more bits than the counter holds? Yes. The new bits that are programmed into the data register shift the old bits out and consequently the last bits that are programmed into the register end up being transferred into the counter Relevant Part: PLL How can the PLL be programmed to have the lock detect signal switch the device out of fast lock? The lock detect signal cannot automatically switch the device out of fast lock. The user must test the part to determine the typical frequency hop time and then program the part to switch out of fast lock after that time has transpired Relevant Part: PLL How can the PLL phase noise be determined? The noise from the PLL is the predominant noise close to the center frequency inside the loop filter bandwidth. The noise is determined by the PLL that is used, the phase comparator frequency, and the output frequency. The formula for calculating the PLL phase noise is: PLL Phase Noise = Normalized Phase Noise (dBc/Hz) + 10 log (Phase Comparator Frequency) + 20 log (N Divide Ratio). The normalized phase noise can be found at National''s Wireless web site. Under the "Selection Guide" heading call up the specific part number under "Single Integer PLLs", "Dual Integer PLLs", or "Fractional-N PLLs". The normalized phase noise is listed for each part. Relevant Part: PLL Is it possible to use the same serial input pins to program multiple PLL devices? Yes. The data can be sent to all PLL devices provided that each PLL has an independent Load Enable (LE) input that controls the transfer of the data to the counters Relevant Part: PLL What VCOs does National recommend to use with National PLL devices? VCOs made by the following manufacturers work well with National PLL devices: Murata, Varil, Alps, and Z-Comm Relevant Part: PLL Why does the Easy PLL Bode plot show a larger closed loop gain than open loop gain? The open loop gain of most systems is defined as the ratio of the system output to the system input without a feedback loop. However the PLL open loop gain is defined as the ratio of the system output divided by the N divide ratio , to the system input. Consequently with a large N divide ratio the open loop gain can be relatively small. At low frequencies the closed loop gain is approximately equal to the N divide ratio, so the closed loop gain can be much larger than the open loop gain. How can the loop bandwidth of an existing PLL loop filter be calculated? To calculate the loop bandwidth, please read AN-1001. Equations 2b and 6, can be used to calculate the loop bandwidth. Also, you can use the easyPLL simulation tool at wireless.national.com. To do this, you need to set up a design and choose a VCO. After you design it, you can edit the VCO gain and loop filter components. Then you can simulate this. If a PLL has an Oscout pin, can it be used to drive the Oscin pin of another PLL? Yes. The internal gate between the Oscin and Oscout amplifies the Oscin signal so the Oscout signal is strong enough to dirve other parts What is the minimum continuous divide ratio of a PLL device? If a user tries to divide by a number smaller than the minimum continuous divide ratio, it may not be possible because there are gaps in the integers that are possible to use. The minimum continuous divide ratio of most National PLLs is (P) X (P-1), where P is the prescaler divide number. Thus if the prescaler is 32, the minimum continuous divide ratio is 32 X 31 = 992. If a user tries to divide by a number smaller than 992, some numbers will be possible to use and some numbers will not be possible to use. However if a user tries to divide by a number greater than 992, all integers will be available to use (up to the maximum number specified for the part). For a quadruple modulus prescaler, please refer to Dean Banerjee''s book entitled "PLL Performance, Simulation, and Design."