SCAN/STA If a system does not have a processor onboard (all processing being handled by a different unit, generating all the information), how could boundary scan be handled using the SCANSTA101 and SCANSTA111? Although the SCANSTA101 and the SCANSTA111 both support the IEEE 1149.1 test bus infrastructure, they both perform two unique functions. The SCANSTA101 is used for vector delivery. Vector deliver can be embedded internally on the system, or it can be from an external source such as the hardware and/or software provided by our third party ATPG partners. The SCANSTA111 is used for scan path management. With the SCANSTA111 you can create a multidrop environment for use with multiple boards, and you can partition scan chains into smaller, more manageable local scan chains. The SCANSTA101 and SCANSTA111 do not have to be used together, although they can be. Relevant Part: SCANSTA101;SCANSTA111 Does the SCANSTA101 need to be located on a board containing a processor, or can it be placed on a different board with communication lines run to the processor? It can be placed on a different board, but, the SCANSTA101 requires Address, Data and control lines. This may be too many signals to route across the backplane. It is possible to put the SCANSTA101 on the other side of a bus adapter, such as a PCI bus adapter. Relevant Part: SCANSTA101 If the boundary scan code were to be stored in the unit, is additional memory required or can the code be stored in the SCANSTA101 IC? Additional memory will most likely be required as the memory on the SCANSTA101 is only about 2KB. The SCANSTA101 memory is only provided as a cache to speed up the vector delivery process by freeing up the processor. Relevant Part: SCANSTA101 Why is there memory in the SCANSTA101? The SCANSTA101 has been optimized for fast vector delivery in applications such as delivering programming or configuration vectors using the 1149.1 bus. Consider interfacing a 16-bit parallel bus operating at 66Mhz to a serial 1149.1 test bus operating at 25Mhz. If the processor is dedicated to this task, then there is a large amount of wait time while the vectors are delivered. In an advanced system, multiple SCANSTA101''s could be used to deliver large amounts of data to multiple 1149.1 scan chains. The memory can be loaded with the vectors, and the processor could manage multiple SCANSTA101''s to obtain the highest vector throughput. Relevant Part: SCANSTA101 How much does the SCANEASE software cost? SCANEASE is free with the use of the SCANSTA101 . The EVF2 that is generated cannot be used with any other device as the functionality and features of the SCANSTA101 are embedded into the binary file. Relevant Part: SCANSTA101 What is the SCANEASE Software? SCANEASE, created by National Semiconductor, is a command line utility that is used to convert (ascii) SVF files (from any ATPG software) into an embedded vector format we call EVF2. The EVF2 is a binary embedded vector format, and it incorporates 1149.1 and the SCANSTA101 features into the EVF2 file. Drivers for the SCANSTA101 read the EVF2 while the I/O drivers deliver the vectors in an embedded environment. Wrappers for a particular embedded environment are provided by the user (i.e.; PCI, PCMCIA, 1553, etc.). Relevant Part: SCANSTA101 How many SCANSTA111''s can you drive with a SCANSTA101? From a DC perspective the SCANSTA111 has a standard CMOS input structure which is a very high impedance. The DC leakage is typically in the order of 10''s of µA. The SCANSTA101 *_SM outputs are all rated to drive 24mA at voltage values that correspond to "1" and "0." Even 30 SCANSTA111 inputs at "10''s of µA" will not overload the output capability of the SCANSTA101 *_SM outputs in the DC case. For the AC case, CMOS inputs are typically modeled as capacitors. Backplanes are modeled as transmission lines and then the system will run at a given frequency. All of this information needs to be taken into account before a design can be finalized. Relevant Part: SCANSTA111;SCANSTA101 Can the SCANSTA111 be placed on the backplane instead of directly on the boards? What are the pros and cons of doing this? Yes it can, however we see nothing positive in doing this, yet on the negative side you''ll be adding pins to the connector between boards and the backplane. The best approach is to place the SCANSTA111 on the board itself. Relevant Part: SCANSTA111 Please explain the state of the SCANSTA111 I/O during the various tristate modes to ensure proper placement of the pull-up or pull-down resistors on the necessary pins. On the Backplane side: TRISTb follows the state of TDOb. When TDOb is TRI-STATE, TRISTb is high. When TDOb is driving, TRISTb is low. TDOb follows the rules set in IEEE Std. 1149.1 (TDOb only drives data during data shift operations and is TRI-STATE at all other times). TDIb, TMSb and TRSTb all have pull-ups per IEEE Std. 1149.1. TCKb does not have any pull-up. On the LSP side: When TDOn is TRI-STATE, TRISTn is high. When TDOn is driving, TRISTn is low. When Local Scan Port n (LSPn) is active, TDOn follows the rules set in IEEE Std. 1149.1 for the TDO pin (TDOn only drives data during data shift operations and is TRI-STATE at all other times). The only situation where TCKn, TMSn, TRSTn, and TCKn are TRI-STATE, is when the OE pin is driven high. At all other times they drive a high or low. There are no pull-ups on outputs. TDIn does have an internal pull-up. Relevant Part: SCANSTA111 Is the SCANSTA101 needed or could the boundary scan be completely controlled from the outside? How could this be implemented? The delivery of 1149.1 vectors can come from an external source such as those provided by the third party ATPG vendors, or you can embed the vector delivery into the system using the SCANSTA101. The strategy you use for the architecture of your particular design would have to be developed based on your end system goals. Initially, at the board level, you probably want to be able to test each board independently using 1149.1. You just need a method to talk to the 1149.1 bus on the board to deliver the test vectors you developed with the ATPG tool. Once the board is in the system - in a backplane with other boards- if you provide a backplane 1149.1 bus, and place a STA111 on each board, you can still test the system using the ATPG tools and hardware for vector delivery providing you can physically get to the 1149.1 connector pins. If you would like to embed this entire test capability into the system, then you need a controller, a master device (SCANSTA101), and a place to store the vectors. Relevant Part: SCANSTA111 Is the SCANSTA111 cascadable? Yes. However, not all Automatic Test Pattern Generation (ATPG) vendors support hierarchy of SCANSTA111 devices, please check with your preferred ATPG vendor Relevant Part: SCANSTA111