Interface What is SPI or Serial to Parallel Interface? The Serial Peripheral Interface Bus (SPI) is a synchronous serial data link standard that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. The Microwire and MicrowirePLUS buses are a subsets of SPI. National offers many solutions with SPI interface including: Low power ADCs Low power DACs Digital Temperature Sensors Audio codec subsystems PLLatinum PLLs and Jitter Cleaners High-Speed Interface and SDI ICs Mobile Pixel Link (MPL) for small-format LCD displays DVGAs Where can I find a utility for converting IBIS models to SPICE? Intusoft offers a free IBIS to SPICE conversion utility. See their Modeling Utilities page, http://www.intusoft.com/utilities.htm. What kind of coaxial cable can be used for Serial Digital Video and similar digital data transmission? Serial Digital Video (SDV) applications normally use precision 75Ω coaxial cables. This cable is designed especially for video applications. Examples of this type of cable are Belden 8281 and 1694A. The construction of cable for SDV is critical to achieving both low error rates and long transmission distances. Coaxial cable for SDV must be of 100% copper construction for both the center conductor and the shield braid. A solid copper center conductor is preferred over stranded as it has a more predictable surface area and skin effect at high frequencies (HF). The shield should be double braid for the most consistent impedance and best shielding effectiveness. Some newer cables use a combination of foil and braid. An inner dielectric of foam polyethylene is preferred for best HF performance and maximum transmission distance. Foam dielectrics are more fragile than solid and require more careful handling and installation. Coax with solid polyethylene dielectric will have poorer HF performance and is generally limited to distances less than 1000 feet (300 meters). Some types of 75Ω coaxial cable such as RG-6/U are intended for RF applications at frequencies greater than 50MHz. Such cables often are made with copper-clad, steel-cored center conductors and/or shield braid. Because of its NRZI encoding, the SDV signal contains frequency components down to DC. Steel-cored cables have high attenuation to the low-frequency and DC component of the SDV signal. This is because the DC resistance of the steel core is much greater than copper. The copper cladding on the steel core is very thin, a few hundreds of microns. Thus, it does not have any effect on conductivity until the signal frequency becomes high enough to where the skin-effect depth is less than or equal to the copper thickness. Cable equalizers cannot compensate for this excess attenuation and the low frequency losses caused by such cables. This leads to poor signal quality, data errors and reduced transmission distances. The remarks about coaxial cable for SDV also apply to any other type of digital data transmission where coding is used that results in a significant DC or low frequency signal content. Examples of such coding are NRZ and NRZI. Relevant Part: CLC001;CLC005;CLC006;CLC007;CLC012;CLC014;CLC020;CLC021;CLC030;CLC031A;LMH0031;LMH0030 Can an LVDS driver be used to drive PECL logic directly? No. LVDS cannot drive PECL without a level translator. Relevant Part: Audio Amplifier How does the CLC001 compare to the CLC005? The CLC001 and CLC005 are high-speed cable drivers with adjustable outputs. There are several differences to note between the two devices. First, the CLC001 is a 3.3V device, while the CLC005 is a 5V device. The CLC005 was designed using a complementary bipolar process, whereas the CLC001 is implemented in a CMOS process. From a switching performance standpoint, the major difference between these two parts is seen at rates of 400 Mbps and above. Both devices are available in an 8-lead SOIC (SOP) package but have different pinouts. The CLC001 has faster edge rates than the CLC005 to further enhance signal quality at high data rates. Rise and fall times are typically 400 ps for the CLC001, while they are 650 ps for the CLC005. The outputs of the CLC001 and CLC005 are similar at low data rates (311 Mbps and below). At higher data rates (400Mbps and above) the difference in the quality of the outputs becomes noticeable. The CLC005 has higher output jitter in this range, which typically limits it to applications running under 500 Mbps. The CLC001 produces a clean eye pattern at data rates to 622 Mbps and beyond. Both cable drivers are intended for use in video, telecom or other applications. They are typically used as single-ended drivers with 75ohm coax cables but they may be used differentially with twisted pair cables. The output load is different for the drivers. The CLC001 requires a 75ohm pull down, while the CLC005 uses a series resistor -- see datasheets for details. Power dissipation is slightly higher for the CLC001 due to the circuit design to accommodate the lower power supply rail. With 1V output swing, power dissipation for the CLC001 ranges from 275mW to 280mW, depending on the data rate being driven. At 800mV output, it’s under 240mW. Power dissipation for the CLC005 is roughly flat over data rate, at 165mW for 1V output, and 160mW for 800mV output across frequency. For this testing both drivers had their proper output loading and were driving a 100-meter cable with a PRBS23 pattern. The CLC001 also features a versatile input stage. Its input stage allows for LVDS and LVPECL levels directly, and PECL levels with attenuation networks. The CLC001 supports the full common-mode range of 0.05V to 3.25V with a sensitivity of 100mV thresholds. The CLC005 is essentially limited to ECL inputs, with a common-mode range of 0.8V to 2.5V below its positive supply. This allows the CLC001 to accept inputs from a wider range of sources. Input biasing with the CLC001 is made easier with a special VBB pin. The VBB pin may be used to bias the inputs to DC voltage levels set by a single resistor to ground. Input biasing for the CLC005 requires more complicated resistor networks, leading to more external components and a larger PCB footprint. In general, the CLC001 requires fewer external components than the CLC005. Even though the class AB output stage of the CLC005 requires no pull-down resistors and the CLC001 implements a high impedance current source output requiring a shunt resistor, both designs use the same number of external components on the output in typical applications (one resistor and one capacitor for AC-coupled output). However, the output level is set by a single resistor to ground on the CLC001, while the CLC005 requires different resistor network schemes to raise or lower the output amplitude. Also, depending upon input termination, the CLC001 may require fewer components on the input. Relevant Part: CLC001;CLC005;CLC006;CLC007 What should be done about the unused output of the CLC001, CLC020, or CLC021? The unused output should be terminated to ensure a balanced output drive. In the typical application circuit, the output sees 75ohms DC-wise and 37.5ohms AC-wise (during transitions). Use a 75ohm pulldown on the unused output to meet the DC condition Relevant Part: CLC001;CLC020;CLC021 Can the output of the CLC001 drive 50ohm loads at full swing? No. It is stated in the datasheet that the CLC001 is designed for 75ohm AC loads, and not intended for 50ohms. The CLC001 is only capable of driving up to 667mV into 50ohms Relevant Part: CLC001 What is the purpose of the VBB pin on the CLC001? The VBB pin is used to provide a DC bias voltage to the inputs for easy AC interfacing. This voltage is determined by a resistor connected between VBB and ground. It may be left unconnected when no bias is needed, as is the case with self-biasing, direct LVDS and LVPECL connections Relevant Part: CLC001 Can the CLC001 act as a level translator, such as in converting LVDS to LVPECL? No. The CLC001 is a cable driver and not a level translator. The CLC001 output cannot DC connect to LVPECL inputs. It must be AC coupled into any ECL device input since it is ground referenced and ECL is positive supply referenced. The CLC001 has a wide input range, accepting both LVPECL and LVDS input swings. Its outputs produce an "LVPECL-like" output. Its outputs are optimized for driving cable in an AC coupled environment, which makes it a very poor translator. Relevant Part: CLC001 Can the outputs of the CLC011 interface to logic levels other than 5V? Yes. The outputs of the CLC011 may be programmed for any voltage level between 3.0V and 5.5V by using the VDP and VCP pins. The data and clock may be set to separate voltage levels Relevant Part: CLC011 How does the CLC011 handle TRS characters that do not comply with SMPTE 259M? The CLC011 will not properly recognize Timing Reference Signal (TRS) characters that do not comply with the SMPTE standards. The CLC011 requires a valid SMPTE 259M TRS signal of 3FFh, 000h, 000h. It uses a brute-force approach of feeding all 30 bits into a shift register and comparing for detection. If those 30 bits are not 3FFh, 000h, 000h, then no TRS is detected Relevant Part: CLC011 How is proper framing applied while using the CLC011 with non-SMPTE data? In the SMPTE application for which this device was designed, the pattern 3FFh, 000h, 000h is used at the start and end of each video line as a Timing Reference Signal (TRS). The CLC011 uses this pattern to determine the framing (where to place the word boundaries). If this pattern is seen in a non-SMPTE application, the CLC011 will readjust its framing and the received words will be shifted. In a non-SMPTE application, an initialization pattern of 3FFh, 000h, 000h should be sent to sync up the CLC011. Then the FE (Frame Enable) input on the CLC011 should be taken to a low state, which will prevent it from realigning the word boundary if it sees this pattern again in the data being transmitted. Relevant Part: CLC011 Can the Carrier Detect output of the CLC014 drive an LED? The Carrier Detect output of the CLC014 is not designed to drive LEDs. A CMOS gate should be added to the Carrier Detect output to accomplish this, as shown in the CLC014 evaluation board Relevant Part: CLC012;CLC014 Does the CLC014 provide an indication of cable length? Yes, the differential voltage measured across the AEC capacitor is roughly proportional to the length of the attached cable. For Belden 8281 coaxial cable this voltage is about 1.5mV/meter Relevant Part: CLC012;CLC014 What is the difference between the CLC014 and the CLC012? The CLC014 and CLC012 are identical in every way except for the carrier detect function. The CLC014 is aimed at SMPTE 259M video applications and employs a simple carrier detect which indicates if a signal is present at the input. The CLC012 is intended for ITU-T G.703 telecom application and employs a Loss of Signal (LOS) detection system that operates according to ITU-T G.775 Relevant Part: CLC012;CLC014 What is the purpose of the CLC014’s output eye monitor (OEM)? The output eye monitor is useful in troubleshooting the CLC014. It shows you the signal coming out of the equalizer block, directly after the filters Relevant Part: CLC012;CLC014 Why are pathological patterns causing problems? The coupling capacitors may be too small. A value of 1µF or higher is necessary to handle the large DC shifts and transitionless intervals present in serial digital video data. Use only high quality RF ceramic capacitors for coupling capacitors. Relevant Part: CLC012;CLC014 Can cable clones be used to test the CLC014? No, all testing must be done using real coaxial cable. The attenuation vs. frequency characteristic of cable clones can differ significantly from that of coaxial cable. Cable clones tend to pass excessive high frequency energy. Since the CLC014 uses the high frequency portion of the input signal to determine how much equalization to apply, the use of cable clones can cause the CLC014 to under-equalize Relevant Part: CLC012;CLC014 How do you connect the output of the CLC014, CLC012, or CLC016 to an LVPECL input? Connecting the output of the 5V CLC014, CLC012, or CLC016, which all have open collector outputs, to a 3.3V LVPECL input presents a number of issues. The main point to consider is that the CLC014, CLC012, and CLC016 have a minimum supply voltage requirement on DO of VCC-1.6V (See the Recommended Operating Conditions in the respective datasheet). The reason being is that the emitters of the output transistors are clamped at about VCC/2, so the output transistors are cut off if you attempt to operate them at a lower DC bias. Three possible solutions are explored: AC coupling. This is the simplest solution, although it is not always possible with all applications. Resistor divider network. There are several problems with using a resistor divider network to shift this voltage down. Since the CLC014/012/016 output is a current sink tied to +5V, any resistive load you put on it to ground will create a standing load current. If you make the standing current small, the resistors from the CLC014/012/016 to ground will be large, and this causes frequency problems. If you make the standing current large, more power is burned in the loads. Either way, the standing current will cause no end of problems to the output transistor. Its operating point will shift due to the new voltage, and the transistor won''t sink its normal current. Dedicated PECL to LVPECL translator. A PECL to LVPECL translator may be used, such as ON Semiconductor''s MC100LVEL92, although this can be a somewhat expensive solution. Relevant Part: CLC014;CLC012;CLC016 Can the CLC014 use transformer coupling? No. The CLC014 is not designed or intended for transformer coupling. The device is specifically designed for capacitor coupling according to SMPTE 259M. Transformer coupling alters the frequency spectrum of the signal. It does not preserve the low frequency energy content and distorts the high frequency content. This causes the CLC014 to under-equalize, along with other, unpredictable effects Relevant Part: CLC014;CLC012 Is it okay to leave the MUTE pin open on the CLC016 when it is not connected to CD? MUTE is an active low signal, so it must be pulled up for an output to be present if it is not connected to the Carrier Detect signal Relevant Part: CLC016;CLC014;CLC012 Does the CLC016 support telecom data rates (SONET/SDH)? Yes. Resistor values are given in the datasheet to allow for auto-rate selection between SONET/SDH data rates. Refer to Table 2 in the datasheet. Relevant Part: CLC016 What are the tradeoffs for the CLC016''s loop filter? Narrower bandwidth makes it more difficult to lock to signals but produces lower residual jitter. Wider bandwidth improves jitter tolerance but increases residual jitter Relevant Part: CLC016 When in fixed rate mode, is the 1nF capacitor attached to ACQ/WR necessary? No. When in fixed rate mode, ACQ/WR is tied high and the capacitor is unnecessary Relevant Part: CLC016 When only using one frequency with the CLC016, what should be done with the other frequency setting inputs? Tie them all together. Relevant Part: CLC016 Can the CLC016 lock to CMI data? Yes. Coded Mark Inversion (CMI) encoded data has transitions on both the rising and falling edge of the clock, so it looks like the data rate is twice that of an NRZ encoded signal. Therefore, when using the CLC016 for 155 Mbps CMI encoded data, it should be set up as if the data rate were 311 Mbps Relevant Part: CLC016 How rapidly does power increase as the CLC018 is expanded to larger array sizes? The power dissipation of expanded CLC018 arrays is dominated by the number of active outputs, so power increases linearly with the array size even though the number of components required increases as the square of the array size Relevant Part: CLC018 Can the parallel clock be applied before the CLC020 or CLC021 is powered up? No, unless the manual reset is used (CLC021 only). In the case of the CLC020, the parallel clock, PCLK, should not be asserted until at least 30µs after power-on. The same is true for the CLC021, unless the manual reset is used. If manual reset is used during power-on, then PCLK may be asserted at any time as long as manual reset is not de-asserted until the part is fully powered. Relevant Part: CLC020;CLC021 What should be done with unused sections of the quad DS26C31 and quad DS26LV31 LVDS drivers? The TTL/CMOS inputs of unused sections of the DS26C31 and DS26LV31 LVDS drivers should be tied to ground. If much more convenient, the inputs may also be tied to Vcc. They should not be left open. The differential LVDS driver output pins should be left unconnected Relevant Part: DS26C31;DS26LV31 What do I do with the unused receivers inputs of the DS26LS32C? We recommend pulling the negative input to ground and the positive input to 2.5 volts (use 17 k Ω resistors pull ups and pull downs). Another option is to use the DS26LS32A where the inputs can be left floating because they have internal pull-up/pull-down resistors). Relevant Part: DS26LS32C What is the output impedance of DS90CP04 output buffers? The DS90CP04 output buffers have less than a 20 Ω output impedance. Consequently, it is not perfectly matched for 100 Ω differential lines. Any reflections caused by impedance mismatches along the line will impose themselves on subsequent data transitions. This will result in increased levels of jitter and lower signal quality - especially at data rates exceeding 1 Gbps. However, if series termination resistors are connected at the device outputs such that the total impedance of the output structure is closer to the impedance of the transmission line, the overall performance of the link will be improved. For 100 Ω differential lines, 43 Ω resistors have been experimentally selected as a good match for series coupling with the DS90CP04 output buffers. Relevant Part: DS90CP04 How do you program the DS90CP04 with a serial interface? The configuration of the internal multiplexer is programmed through a simple serial interface consisting of a serial clock (SCLK) and a serial input data line (SI/SEL1). This serial interface provides a method for easy expansion into a larger switch array. A replicated output serial interface (RSCLK, RSO) is provided for propagating the control data to a downstream device in the row of an array of DS90CP04 devices in a matrix. A similar replicated serial interface (CSCLK, CSO) is provided for propagating the control data to downstream devices in the first column of the device matrix. By using this scheme, the user can program all devices in the matrix through one serial control bus (SCLK and SI/SEL1) and use of the feedthrough replicated control bus at RSCLK and RSO, CSCLK and CSO. To program the configuration of the switch, a 30-bit control word is sent to the device. The first 6 bits shift the start frame into SI. The only two valid start frames are 1F’h for a configuration load and 1E’h for a configuration read. The start frame is followed by the row and column addresses of the device to be accessed, as well as the switch configuration of the four channels of the device. For a more detailed explanation, please refer to page 13 of the DS90CP04 datasheet. Relevant Part: DS90CP04 Are there any power-up sequence requirements for National''s Channel-link transmitters? Yes, use the following power-up sequence for the DS90CR217 and DS90CR287: Apply power while holding the powerdown (PD) pin LOW → Apply clock→ assert PD pin HIGH. In this sequence the PLL is held off until a valid clock is applied. OR Apply clock → Apply power. In this sequence, the part starts up with a valid clock at the PLL input. DO NOT Apply power → PD Pin = HIGH (device enabled) → (after a delay) Apply clock. This can cause a miss start and corrupt the LVDS output clock and data. AND DO NOT Apply PLLVcc before Vcc and LVDSVcc. The three Vcc''s can power up at the same time. For the DS90CR485, use the following power-up sequence: Apply all Vcc’s at the same time and then apply Clock. OR Apply Vcc3V → Apply other Vcc''s → Apply Clock → Assert PD pin = HIGH Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Are there any suggestions for using Spread Spectrum Clocking with National’s Channel Link devices? Down Spectrum is best. Avoid center or up spectrum and carrier frequencies over 200 kHz are not recommended. PLLs tend to track in the 50 to 100kHz range. It is recommend to use smaller spread spectrum percentages - typically 1 and 2% are used while 3.5% borders on the higher side. On the higher side, the rate of change between PLL sampling positions may become too great and cause errors. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Can Channel Link devices be used with Spread Spectrum Clocks? We do not provide test coverage for spread spectrum applications. However, Channel Link devices have been used by customers in spread spectrum clock applications without any tracking problems. Due to inherent PLL filtering effects, PLLs will help reduce the effect of spread spectrums -- especially in the transmitter since the LVDS output clock is generated from the PLL. The receiver PLL is used to strobe incoming data whereas the LVDS clock is more or less only buffered and delayed. As a result, the receiver PLL has an almost unity gain jitter transfer curve. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Can multiple channel-link chipsets be used on a wider bus application? Yes, but the clock to data skew must be within the downstream receiver setup and hold time limit in order for the receiver to sample data correctly. Assuming the lengths of all interconnects are equal, the determining factors for skew between clock and data are the latency of the transmitter, latency of the receiver and the receiver setup / hold time. Thus, Downstream Rx Tsetup < RSRC – [(TPDL_max + RPDL_max) – (TPDL_min + RPDL_min)] And, Downstream RX Thold < RHRC – [(TPDL_max + RPDL_max) – (TPDL_min + RPDL_min)] Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 How are pre-emphasis levels adjusted in channel-link transmitters? The PRE pin requires one pull-up resistor to Vcc in order to set the DC level. Therefore, the pre-emphasis level can be adjusted by changing the pull-up resistor value. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 How do Channel-link receivers generate strobe positions? The receiver generates strobe positions based on the rising edge of the PREVIOUS clock cycle. Strobes are resynchronized for each new clock cycle; therefore, cycle-to-cycle jitter on the receiver input clock should be minimized. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 How do I calculate RSKM? RSKM = Tppos_max – Rspos_min This formula takes into account the transmitter pulse positions (Tppos_min and Tppos_max) and the receiver input setup and hold time (internal data sampling window - Rspos_min and Rspos_max). Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 How does the DC Balance mode work? In DC Balance mode, an additional bit is transmitted on every LVDS pair each clock cycle. The value of the DC balance bit (DCBAL) is 0 when the data sent is unmodified and 1 when the data sent is inverted. To determine whether the sent data is unmodified or inverted, the running word disparity and current word disparity are used. These equations and parameters are used to determine DCBAL: (C) = Current word disparity = > -1 for every data bit LOW +1 for every data bit HIGH (R) = Running word disparity = > -1 for every UNMODIFIED data bit, +1 for every INVERTED data bit. -6 ≤ (R) ≤ +7   DCBAL = 1 (inverted) if C AND R = + DCBAL = 1 (inverted) if R = – AND C = – or 0 DCBAL = 1 (inverted) if R = 0 DCBAL = 0 (unmodified) if R = + AND C = – or 0 DCBAL = 0 (unmodified) if R = – AND C = + Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 How is DC Balance mode enabled? DC Balance mode is enabled by pulling the BAL pin of the transmitter to HIGH. If the DS90CR486 receiver is used, the BAL pin of the receiver must also be HIGH to enable DC Balance mode. The DS90CR482 and DS90CR484 receivers are designed to automatically detect the DC Balance or non-DC Balance transmitted data from the transmitter, so no action is required. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Is there a channel-link chipset optimized for a 48-bit bus at 60MHz - 70MHz? Yes. The DS90CR481 and DS90CR482 chipset support 48-bit bus widths from 55MHz – 70MHz operation. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Is too much pre-emphasis a concern when designing with channel link products? In general, too much pre-emphasis can cause over or undershoot at the receiver input pins. This can result in excessive noise and increased power consumption. When routing through connectors or poorly designed boards, pre-emphasis can create crosstalk. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What causes receiver input clock cycle-to-cycle jitter? Any jitter from the transmitter output clock will be passed to the receiver input clock. As a result, it is important to keep the transmitter output clock cycle-to-cycle jitter (TJCC) to a minimum. Possible sources of noise that can increase transmitter output cycle-to-cycle jitter include power supply noise, and cycle-to-cycle jitter from oscillators, FPGAs or other clock sources used at the transmitter input. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What do I need to know about activating DESKEW? To use DESKEW, the DESKEW pin must be activated whenever the receiver is powered up first, and DESKEW must be reactivated if power is lost, or if the cable has been switched or disconnected. When the receiver is performing the “DESKEW” function, all receiver data outputs are set to a LOW state. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What happens if input edge rates to the transmitter exceed datasheet specifications? The device will still function with input edge rates faster than the datasheet specification; however, it is not recommended for these reasons: Extremely fast edge rates tend to ring and have over / undershoot. It creates more noise into the chip resulting in more jitter. If the over or undershoot exceeds the ABS-MAX datasheet specification, the ESD protection path could turn on causing excess current to flow. Extremely fast edge rates have a very fast dv/dt that couples more noise into the chip and creates more common-mode noise on the LVDS outputs. This results in higher EMI levels. However, the data is not impacted as it is differential. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What is DESKEW? “DESKEW” is a calibration function that compensates for skew between data signals, with respect to the rising edge of the LVDS clock, on each of the independent differential pairs (pair-to-pair skew). The “DESKEW” function will compensate a maximum of +/-1 LVDS data bit time from the ideal strobe location. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What is RSKM? RSKM is the Receiver Input Skew Margin. It is defined as the valid data sampling region at the receiver input. This specification provides timing budget information for LVDS interconnect skew, Inter-Symbol Interference, and source clock cycle-to-cycle jitter. RSKM > Interconnect skew + ISI + cycle-to-cycle clock jitter Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What is TJCC? TJCC is the cycle-to-cycle clock jitter for the Channel-link transmitter output clock. Any jitter introduced to the transmitter input clock (TxCLKIN) can potentially pass on to the transmitter output clock. National Semiconductor’s 3V Channel-link transmitters have been redesigned to enhance the rejection of cycle-to-cycle jitter. Consequently, cycle-to-cycle jitter at the transmitter clock input (TxCLKIN) is no longer directly passed to the transmitter output clock (TxCLKOUT). Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What is pre-emphasis? Pre-emphasis is a feature that adds extra energy during LVDS logic transitions to reduce the effects of cable loading and attenuation. For channel-link transmitters, the pre-emphasis level is set via a DC voltage level from 0.75V to Vcc that is applied at the PRE pin of the device. Higher input voltages on the PRE pin increases the magnitude of dynamic current during data transition. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What is the DC Balance mode? DC Balance mode is supported by all 48-bit channel-link chipsets. It is a data transmission mode that selectively sends data either unmodified or inverted. The purpose of the DC Balance mode is to minimize the short AND long term DC bias on the signal caused by long streams of ones or zeros. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What is the latency of the DS90CR285 and DS90CR286A? The DS90CR285 has a latency of 1 clock period plus 5.5 ns max. The DS90CR286A has a latency of 2 clock periods plus 7.5 ns max. Total interconnect latency is Tx Latency + Rx Latency + interconnect flight time. This is slowest at 20MHz (50ns cycle time), being (1x50ns + 5.5ns) + (2x50ns + 7.5ns) + interconnect flight time = 163ns + interconnect flight time. Clearly this will be much less at 66MHz (15.15ns cycle time), being (1x15.15ns + 5.5ns) + (2x15.15ns + 7.5ns) + interconnect flight time = 58.5ns + interconnect flight time. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What should be done with un-used Channel Link input pins? Un-used input pins for transmitters may be tied to ground or left open. Some transmitter inputs have internal pull-down resistors. For details, please consult the datasheet. Un-used input pins for the receivers should be left open. The internal fail-safe circuitry of the receiver input will pull the receiver output high to avoid unnecessary switching on the outputs. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What should be done with un-used Channel Link output pins? Un-used output pins should be left floating. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 What value pull-up or pull-down resistors should be used with Channel Link devices? Pull-up or pull-down resistors should be in the 1kΩ: to 2kΩ. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Which receivers support DESKEW? Only 48-bit channel-link receivers support the “DESKEW” function and the level of support varies from receiver to receiver; therefore, consult receiver datasheets to determine the level of “DESKEW” supported. Below is a summary of “DESKEW” support/requirements vs. receivers: DS90CR482/DS90CR484 “DESKEW” only supported in DC Balance mode. DESKEW pin must set to HIGH to activate “DESKEW” Transmitter’s DS_OPT pin must be LOW for a minimum of 4 clock cycles. During this period, the transmitter will transmit a series of “calibration patterns”. Data will not be transmitted until the DS_OPT pin of the transmitter is HIGH. “DESKEW” is supported up to 80MHz. DS90CR486 “DESKEW” is done automatically when the device is first powered up. “DESKEW” is supported in both DC Balance mode and non-DC Balance mode. DESKEW and CON1 pins must set to HIGH upon powering up. “DESKEW” function can be re-activated by pulling the DESKEW pin LOW for a duration greater than one clock cycle. Transmitter’s DS_OPT pin can be set HIGH or LOW “DESKEW” can be performed with any data pattern with a transition over a period of three clock cycles. "DESKEW” is supported for the entire operating frequency range Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Why are part latencies described in multiple clock cycles? The transmitter and receiver are synchronous devices that have multiple register stages used during the serialization/deserialization of the data. Relevant Part: DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 How well does the DS92LV18 perform in cable drive applications? The DS92LV18 can be used in cable drive applications with limited capability. If employed to transmit data across a generic category 5 cable, it can operate at its highest operating frequency (66 MHz) with cable lengths up to 10 ft. To transmit the data across longer links, cables with lower nominal attenuation are required. The Belden 89207 20 AWG twin-ax cable has proven to be a solid performer. At 66 MHz operation (1.32 Gbps data rate), the DS92LV18 can drive the Belden 89207 cable up to 20 ft. Careful interconnect design should be implemented to maximize the cable drive capabilities of the DS92LV18. Selecting controlled impedance cables and connectors greatly increases the chance for an error-free data transfer. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What is the output impedance of the DS90CP04 output buffers? The DS90CP04 output buffers have less than 20Ω output impedance. Consequently, it is not perfectly matched for 100Ω differential lines. Any reflections caused by impedance mismatches along the line will impose themselves on subsequent data transitions. This will result in increased levels of jitter and lower signal quality - especially at data rates exceeding 1 Gbps. However, if series termination resistors are connected at the device outputs such that the total impedance of the output structure is closer to the impedance of the transmission line, the overall performance of the link will be improved. For 100 Ω differential lines, 43Ω resistors have been experimentally selected as a good match for series coupling with the DS90CP04 output buffers. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 Does National Semiconductor provide models for its LVDS devices? National Semiconductor provides IBIS models for all LVDS devices as they are released. National recognizes the importance of providing quality IBIS models to its customers, and fully supports the IBIS standard. Models released prior to March of 2002 support IBIS version 2.1, whereas models released afterward are compatible with IBIS version 3.2. National Semiconductor continuously improves IBIS model accuracy and strives to be an active participant within the IBIS community. To obtain IBIS models for National Semiconductor’s LVDS devices and to learn more about IBIS, please visit National''s IBIS models site Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 Can National Semiconductor''s LVDS receivers guarantee proper failsafe operation in extremely noisy environments? The internal failsafe circuitry is designed to source/sink a very small amount of current, providing failsafe protection for floating inputs, shorted receiver inputs, and terminated receiver inputs as described in the component’s datasheet. It is not designed to provide failsafe in noisy environments such as when the cable is disconnected from the driver’s end or if the driver is in tri-state. When this happens, the cable becomes a floating antenna that can pick up noise. If the cable picks up more noise than the internal failsafe circuitry can handle, the receiver may switch or oscillate. If this condition can happen in your application, it is recommended that you choose a balanced and/or shielded cable that will reduce the amount of differential noise on the cable. In addition, you may want to add external failsafe resistors to create a larger noise margin. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 Does National Semiconductor offer any cross-point switches? National Semiconductor currently offers several smaller-size digital Crosspoint switches. Click here for a complete list Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 How can I calculate the power dissipation of the DS90CP04 in my application? Power supply current (IDD) of the DS90CP04 varies depending on the number of LVDS inputs and outputs used. It can be quickly estimated using the following empirically extracted formula: IDD = 18*(1+M) +42*N [mA] In the equation shown above, M is the number of LVDS inputs and N is the number of LVDS outputs used. Here is an example: If an application requires a quad repeater where all inputs and outputs are utilized (M=4 and N =4), the IDD estimator formula will yield 258 mA. Once IDD value is estimated, a simple multiplication with the VDD value will give you an estimated power dissipation. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 How do I optimize my PCB layout for reduced EMI? The two most important factors to consider when designing differential signals for low EMI are close coupling between the conductors of each differential signal pair and minimizing the imbalances between the conductors of each pair. In order for sufficient coupling to occur, the space between the conductors of a differentia pair should be kept to a minimum. The best practice is to use the closest spacing between the differential traces allowed by your PCB vendor and then adjust trace width to control differential impedance. In order to have minimal imbalances between the conductors of each pair, any impedance discontinuity such as vias, connectors, PCB traces, etc., should be introduced equally to both members of the pair. When the differential pair travels through the pin field of a connector it is important to maintain differential coupling. A lack of coupling in this critical design area will result in increased crosstalk and reduced system noise margin. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 How does Low Voltage Differential Signaling (LVDS) compare to other differential interface standards? LVDS is a current loop signaling technology in which the current loop direction (clockwise or counter-clockwise) determines the logic level (high or low). Approximately 3.5mA is driven down one wire of the pair and returns through the other wire of the pair. A voltage (approx. +/-3.5mA x 100Ω = +/-350mV) is generated across the termination resistor. The receiver, a differential comparator, measures the polarity of this voltage drop, positive voltage corresponding to logic high and negative voltage to logic low. LVDS provides the smallest swing of 350mV and a robust common-mode range of +/-1V around its offset voltage (VOS). Some devices are specified to have a common mode range that meets or in some cases exceeds the supply voltage. LVDS is primarily used for point-to-point or multidrop applications with certain flavors like Bus LVDS (BLVDS) and Multipoint LVDS (MLVDS) supporting multipoint configurations. Due to the output current and edge rates, LVDS is targeted for the DC to 2Gbps range. It also tends to be the lowest power of the three. LVPECL provides a 700 to 800mV output swing. Depending upon the receiver used, it may have similar thresholds and common-mode range as LVDS, but tends to be more restrictive. It is also versatile and can support point-to-point, multidrop, or multipoint applications. ECL operates from DC to >10Gbps depending upon the family. CML provides an 800mV swing in certain implementations. Being highly vendor specific, many parts offer control of the output swing and the 800mV may be adjustable down to a few hundred millivolts to minimize crosstalk. CML is for point-to-point links only and provides matched source and load terminations. This greatly simplifies the interconnect and stub lengths (termination to RX input) are minimized, thus signal quality is optimized. Due to the fact that one side is pulled to the rail, both the driver and receiver should be powered from the same supply potential for DC coupled applications. This is one reason that AC coupling is popular with CML interfaces. It provides common-mode tolerance, fault protection and also supply independency. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What advantages does National Semiconductor BLVDS have over LVDS I/O integrated into the latest FPGA''s? Discrete BLVDS devices use a standard 3.3V supply level. Often times LVDS I/O on an FPGA will require a 2.5V supply level. The additional regulation and board space consumed more than offsets the area and power consumed with a 3.3V discrete solution. The pinout used for discrete LVDS products offers easy routing to all popular connector styles. The ability to cleanly route signals to and from a connector allows the discrete LVDS devices to be placed in close proximity to connectors or other IC’s. Placing discrete transceivers close to the connector dramatically improves the signal integrity of the backplane interface. Bus LVDS devices often tout ESD performance well in excess of 4Kv. This robust ESD performance enhances the reliability of any system. FPGA’s that do not have true complimentary outputs require attenuation networks to achieve LVDS like switching levels. This solution requires two LVCMOS FPGA outputs to drive the attenuation network doubling the internal dynamic power of the FPGA. This also puts additional stress on the board-decoupling scheme. In addition, the complementary outputs are no longer 180 degrees out of phase or exactly opposite each other. Perfectly opposite fields will tend to cancel each other out. This additional phase shift due to the implementation in the FPGA will allow some of the signal energy to be more easily radiated as EMI. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What are the benefits of LVDS (Low Voltage Differential Signaling) Technology? High Speed - The transition time of a signal is a limit of how fast you can go. A larger signal swing will take a longer time to transition. One solution to go faster is to decrease the transition time, but that is not practical due to noise, crosstalk, EMI and power reasons. To gain speed, another solution is to lower the swing, resulting in much faster transition times. This can also reduce noise margins, but LVDS solves this problem by using a differential transmission scheme where the signal-to-noise ratio is greatly improved. Low EMI – Relatively constant, small output current lowers power/ground noise and since the current in the signal pair is a closely-coupled current loop, fringing electric fields tend to cancel, reducing EMI. Low Power - One of the primary goals of LVDS is LOW POWER dissipation. This has been achieved by using a CMOS process to minimize static current draw. The driver design is current-mode, thus switching spikes are greatly reduced. This lowers EMI, simplifies power distribution and bypassing requirements. Also the Icc vs. frequency curve is very flat. For a voltage mode driver on the other hand, power supply current (Icc) dramatically increases with frequency and thus the device is typically limited to <50MHz operation. Even with a 300 ps transition, slew rate is kept to about 1V/ns. 330mV across the 100 ohm load, requires a load current of only 3.3mA. LVDS addresses static and load current, providing the lowest power interface and enabling higher levels of integration without heat slugs hidden in the packages! Three words to remember for power: Static – Continuous power consumption Dynamic – Frequency dependent power consumption Load – Power delivered to the receiver Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What is failsafe? Failsafe is a feature of an LVDS receiver that ensures a known state of its outputs in cases when a fault condition occurs. National Semiconductor’s LVDS receivers may provide failsafe support for open, shorted and terminated LVDS inputs. When the failsafe circuitry detects any of these fault conditions, it sets the LVDS non-inverting output pin (OUT+) to a static HIGH (typically 1.4 V for LVDS), and its complement, inverting output pin (OUT-), to a static LOW (typically 1.0 V for LVDS) voltage level. This is a +400 mV differential signal. Some devices may also have a loss-of-signal (LOS) reporting pin available. In this case, when a fault condition occurs, the device sets the LOS pin to a logic LOW level to inform that a failsafe condition of the line is present and that the LVDS outputs are placed into the failsafe mode. The following describes typical faulty cases at the input of a receiver and the receiver response to fault condition. Open Input Failsafe When the receiver inputs are floating (non-terminated), the impedance between pins is very large. This can occur in certain multi-drop applications where a card is removed from the bus. In this case, the receiver inputs are biased by weak current sources so that the pins are brought to the same potential. The failsafe circuitry will detect this failsafe condition and place the LVDS outputs into the failsafe mode and also sets the LOS pin to a logic LOW state. Terminated Input Failsafe This is when the receiver input pins are terminated by a resistor and no active LVDS signal is applied. This occurs when the driver is powered-off, tri-stated, or removed from the line. The failsafe circuitry detects this condition at the receiver inputs, puts the LVDS output pins into the failsafe mode, and sets the \LOS pin to a static LOW state. Shorted Input Failsafe When this fault condition occurs an interconnect fault has shorted the lines together resulting in a 0 V differential input voltage. The failsafe circuitry will guarantee a known state at the LVDS outputs and set the \LOS pin to a static LOW state. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What is important when selecting an LVDS cable driver? For cable drive applications, there are several important characteristics to consider before selecting a LVDS driver. One of them is the edge rate. Since cable losses will attenuate the signal as well as slow down the transitions, the LVDS drivers with faster falling and rising times will generally be capable of transmitting a signal across longer cables. Devices with larger differential output voltage, VOD, will also have increased margin for driving long cables. Finally, pre-emphasis is a highly desirable feature of an LVDS driver for applications that utilize very lossy cables or large backplane. The pre-emphasis increases the high frequency content of the signal to compensate for the transmission media losses. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What is pre-emphasis and receive equalization? Transmit pre-emphasis, is a method used to boost the high-frequency content of the output signal relative to the DC signal amplitude. This boost in high-frequency content serves to effectively compensate for the frequency dependent loss the signal incurs as it propagates to the receiver. A transmit pre-emphasis is used to overcome the high frequency attenuation in the connectors and trace. Another method, receive equalization, is a function applied at the receiver intended to counteract the degradation of signal strength over a long transmission line or cable run. In demanding applications that exhibit a large signal loss it may be necessary to combine transmit pre-emphasis and receive equalization for effective high-speed communication. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What is the difference between BLVDS (Bus Low Voltage Differential Signaling) and MLVDS (Multipoint Low Voltage Signaling)? National Semiconductor was involved in the development of the MLVDS standard. The backbone of the standard has been written around the BLVDS devices from National that has been used so effectively for over 5 years. The MLVDS standard has added an additional specification to increase the input common mode range. BLVDS devices can operate in applications where the ground potential between devices is up to a volt apart. The MLVDS device’s additional common mode range will allow them to operate in applications where the ground difference is up to 2 volts apart. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What is the difference between LVDS (Low Voltage Differential Signaling) and BLVDS (Bus Low Voltage Differential Signaling)? The major difference between BLVDS and LVDS is that Bus LVDS drivers use a higher (10mA) current drive output circuit. The higher drive allows BLVDS devices to drive heavily loaded fully populated multipoint backplanes. In addition to the higher drive, BLVDS devices have slower output edge rates to reduce reflections caused by stubs in multipoint backplane applications. Both technologies have 100mV input sensitivity, fully differential signal swings, and high levels of ESD immunity. National Semiconductor LVDS and BLVDS devices allow for easy hot-insertion and high impedance power down in high reliability applications. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What is the maximum speed for LVDS (Low Voltage Differential Signaling) Technology? The need for speed is real and increasing at a tremendous rate every year. As processors get faster and faster, bus speeds increase to service them. As speed goes up, timing margins shrink – thus the need for high-performance interface devices. Remember the days of text only messages? Today you get icons, images, and loads of attachments on every email – thus the demand for bandwidth is pushed from the desktop thru the datacom and telecom networks. Low Voltage Differential Signaling (LVDS) is specified in standard ANSI/TIA/EIA-644-A-2001 (this is a revision of past ANSI/TIA/EIA-644 versions). This standard specifies LVDS electrical signaling levels only—medium and application are up to the user, making LVDS useful in a wide variety of applications. In fact, many system standards refer to LVDS for the signaling scheme. The actual maximum speed of operation will depend on many factors. Below is a rough guideline for some typical bus topologies. In point-to-point applications the fastest LVDS devices can operate at 2Gbps. In limited multidrop applications with a single driver and 2-3 receivers BLVDS can achieve speeds of up to 800Mbps. In larger multidrop applications with a single driver and 10+ receivers BLVDS can achieve speeds of up to 400Mbps. In larger multipoint applications with 10+ transceivers BLVDS can achieve speeds of up to 300Mbps. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What is the proper termination for a BLVDS backplane? A bus designer will determine the Bus LVDS termination resistor (RT) value by calculating the loaded impedance (ZL) of the bus. There are complex sets of variables that determine the ZL. The factors are the spacing between the loads, or plug-in cards, and the characteristic impedance (Zo) of the backplane trace. In addition, the loading from the plug-in card stubs, connectors, and transceiver loading also affect the ZL. For understanding purposes only—and not an actual calculation—assume a backplane with Zo =100Ω, 30 mm spacing between 20 slots, 30 mm stub lengths, 2 mm style connectors, and National’s DS92LV010 Bus LVDS Transceiver on all cards. In this case, the ZL is about 54Ω. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What is the recommended de-coupling scheme for LVDS drivers and receivers? Bypass capacitors must be used on all power pins. High frequency ceramic (surface mount is recommended) 0.1 µF and 0.001 µF capacitors should be used and placed in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10 µF (35 V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 Where should I use National Semiconductor''s Crosspoint switches? National Semiconductor cross-point switches are well suited for telecommunication switching equipment and other large communication backplanes to facilitate low power, high speed data transmission for point to point interconnects. They are the ideal candidates for the distribution of a serial bus across several rack-mounted backplanes. This is due to their repeater and signal splitter capabilities. The non-blocking architecture allows them to connect any input to any output or outputs. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 Why does BLVDS (Bus Low Voltage Differential Signaling) use a 10mA current source? BLVDS can drive a heavily loaded bus with only 10 mA because it also minimizes the bus loading from other transceivers attached to the bus. Another benefit to the overall system is the low cost of termination and the low power dissipated at the termination. Bus LVDS does not require any active devices for the termination. Unlike GTL, SSTL, or TTL, Bus LVDS uses only 2 passive termination resistors. All other bus-driving technologies require a tightly regulated termination voltage, such as 1.5V for GTL+. This tight regulation adds substantial cost to the backplane design because of the required voltage control chips and passive components that surround the chips. However, why add voltage regulation when the Bus LVDS only requires that you have two passive resistors? A bus designer will determine the Bus LVDS termination resistor (RT) value by calculating the loaded impedance (ZL) of the bus. There are complex sets of variables that determine the ZL. The factors are spacing between the loads—or plug-in cards– and the characteristic impedance (Zo) of the backplane trace. In addition, the loading from the plug-in card stubs, connectors, and transceiver loading affect the ZL. For understanding purposes only—and not an actual calculation—assume a multi-drop backplane with Zo =100Ω, 30 mm spacing between 20 slots, 30 mm stub lengths, 2 mm style connectors, and National’s DS92LV010 Bus LVDS Transceiver on all cards. In this case, the ZL is about 54Ω. This ZL would be terminated on both ends of the bus with 27Ω resistors. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 Why does National Semiconductor call its DS92001 buffer a ''stub-hider''? The DS92001 has edge transitions optimized for multidrop backplanes where the switching frequency is in the 200 MHz range or less. The output edge rate is critical in some systems where long stubs may be present, and utilizing a slow transition allows for longer stub lengths. In addition, the device is packaged in a small 8-pin SOIC package that can be placed very close to the main transmission line. This reduced stub length dramatically improves the performance of the backplane. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 How do you program the DS90CP04 with a serial interface? The configuration of the internal multiplexer is programmed through a simple serial interface consisting of a serial clock (SCLK) and a serial input data line (SI/SEL1). This serial interface provides a method for easy expansion into a larger switch array. A replicated output serial interface (RSCLK, RSO) is provided for propagating the control data to a downstream device in the row of an array of DS90CP04 devices in a matrix. A similar replicated serial interface (CSCLK, CSO) is provided for propagating the control data to the downstream devices in the first column of the device matrix. Through this scheme, the user can program all the devices in the matrix through one serial control bus (SCLK and SI/SEL1) and use of the feedthrough replicated control bus at RSCLK and RSO, CSCLK and CSO. To program the configuration of the switch, a 30-bit control word is sent to the device. The first 6 bits shift the start frame into SI. The only two valid start frames are 1F’h for a configuration load and 1E’h for a configuration read. The start frame is followed by the row and column addresses of the device to be accessed, as well as the switch configuration of the four channels of the device. For a more detailed explanation, please refer to page 13 of the device datasheet. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What are the general PCB design recommendations for National Semiconductor''s Interface Devices? Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals. Dedicating planes for VCC and Ground are typically required for high-speed design. A solid ground plane is required to establish a controlled (known) impedance for the transmission line interconnects. Narrow spacing between power and ground planes will also create an excellent high frequency bypass capacitance. Isolate fast edge rate CMOS/TTL signals from LVDS signals, or they may couple crosstalk onto the LVDS lines. It is best to put TTL and LVDS signals on a different layer(s) which should be isolated by the power and ground planes. Keep drivers and receivers as close to the (LVDS port side) connectors as possible. This helps ensure that the differential lines do not pick up noise generated from the board, which can result in higher EMI. This recommendation also helps to minimize skew between the lines. Bypass each LVDS device and also use distributed bulk capacitance. Surface mount capacitors placed close to power and ground pins work best. Power and ground traces should be wide (low impedance) traces. Do not use 50Ω· design rules for power and ground traces. Their function is to be a low impedance path. Keep ground PCB return paths short and wide. Provide paths that create the smallest return loop for image currents. Systems connected through cables should provide a common ground wire between the systems. This provides a short known path for common-mode currents to return. Use two vias to connect bypass capacitor pads to power and ground planes. This minimizes inductance effects. Surface mount capacitors are recommended since they are compact and can be located close to device pins. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 What is important when selecting cables and connectors for LVDS? When choosing cables and connectors for LVDS it is important to remember the following: Use controlled impedance media. Choose cables and connectors that have a differential impedance of 100#8486;. This should minimize major impedance discontinuities that cause signal reflections. Balanced cables (twisted pair) are usually better than unbalanced cables (ribbon cable, multi-conductor) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects. They also tend to pick up electromagnetic radiation as common-mode (not differential-mode) noise, which is rejected by the receiver. For cable distances < 0.5m, most cable types can be used effectively. For distances 0.5m < d < 10m, CAT 5 (Category 5) twisted pair cable works well, is readily available, and is relatively inexpensive. Other types of cables may also be used for specific applications. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486;EQ50F100 The LVDS transmitter seems to be working, but I see alot of jitter on the LVDS outputs. Check the TCLK input pin for excessive jitter. Any jitter seen on the TCLK input will also pass onto the LVDS outputs. Also, make sure adequate bypassing is available on the power pins. As a general rule of thumb, there should be less than 100mV of noise on the power pins. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 How do the embedded clock receivers continue to recover a RCLK when I stop sending data on the transmitter side? Once the transmitter PLL is locked to the TCLK, it continues to send a clock bit. If no data is present at the TTL inputs, these pins have internal pull-downs that will provide an all 0 data pattern (with the exception of the start bit) at the LVDS outputs. Customers can use the DEN pin to disable the LVDS outputs, but the LVDS receiver will need to relock to the incoming data stream. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Is there any phase relationship between REFCLK and RCLK? No. REFCLK is only used at start-up, or after loss of lock, by the receiver PLL to strobe the incoming serial data stream for the embedded clock. On the other hand, RCLK should be used by the customer to strobe the recovered data (ROUTx). Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Is there any phase relationship between TCLK and REFCLK? No. There is no phase relationship between the two. However, their frequency must be within +/- 5% of each other. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Why do I receive incorrect data when I perform a Bit Error Rate Test (BERT)? Are the setup/hold times on the transmitter input pins being met? Is the SYNC pin high or low? Is the BERT tester expecting to receive a SYNC pattern? The SYNC pin should be low for normal data transfer operation. Is the RCLK being used to strobe the recovered data? Lastly, where applicable, verify both the transmitter and receiver are set to strobe on the same edges (e.g. Rising or Falling). Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Why does my LVDS receiver not lock to the incoming data stream? Is the LVDS link terminated with an appropriate termination scheme (Please see the LVDS Owner''s Manual for proper termination techniqes)? Are RMT patterns (please see datasheets for a description of RMT patterns) present? Is the receiver powerdown pin biased correctly? Is the REN pin enabled? Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Why does the LVDS receiver occasionally provide a RCLK and recovered data (ROUTx), even though my cable is not connected? Noise is coupling onto the LVDS receiver input pins. Are TTL signals routed near by? Are the LVDS lines closely coupled for better common-mode noise rejection? Fail-safe biasing can be added to the LVDS input pins to help reject noise. Please see the LVDS owner''s manual and Application Note 1194 "Failsafe Biasing of LVDS Interfaces" which are available on our website for details on proper failsafe biasing. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16;DS90CR217;DS90CR287;DS90CR213;DS90CR214;DS90CR215;DS90CR216;DS90CR217;DS90CR218;DS90CR283;DS90CR284;DS90CR285;DS90CR286;DS90CR287;DS90CR288;DS90CR481;DS90CR482;DS90CR484;DS90CR485;DS90CR486 Are National''s receiver and transceiver products hot-plug devices? Yes. We guarantee hot-plug insertion support for all of our receiver and transceiver products. Typically, this feature is not recommended for transmitters. The correct contact order for hot-plugging devices should be ground, power, and then I/O''s. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 Are bypass capacitors required for systems designed with LVDS technology? Yes. No matter how simple the design, bypass capacitors are always recommended. Please see product datasheets for bypass suggestions. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 Can CAT5 cable be used as the interconnect, although the data rates advertised by your parts seem to be faster than what CAT5 cable is rated for? LVDS signaling works well on CAT5 and many other types of cables. Many of National''s LVDS drivers and receivers are capable of driving data rates up to approximately 1.2Gbps over CAT5 cable. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 Can I ever send a repetitive multi-transition (RMT) pattern? If RMT patterns are present upon power-up, enable the SYNC mode (SYNC pin = HIGH) to establish lock between the transmitter and receiver. Once the receiver is locked (LOCK* pin = HIGH), any type of data pattern may be sent. This includes RMT patterns. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 Can LVDS components be used in Fiber applications? Yes. We recommend all of our serializer and deserializer parts with fiber or AC-coupling as long as the customer guarantees they have enough transitions to keep the DC offset balanced. For example, customers can use 8b/10b coding with the 10-bit serializer and deserializer parts to keep the DC balance, or they can use a scrambling technique such as that used in the Utopia Bridge or Packet Bridge. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 Can LVDS devices only be connected through backplanes? No. LVDS signaling can also be transmitted through different types of cables. Even low-cost CAT5 cables can be used with reliable performance. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 Can LVDS parts be AC-coupled? Yes. However, when AC-coupling LVDS signals, the common-mode voltage component of the signal is lost. A voltage biasing resistor network may be required for some receivers to work properly. To optimize AC-coupled applications, LVDS signals will require some type of data scrambling such as 8b/10b coding. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 Can parts be daisy-chained by connecting the recovered clock (RCLK) of a receiver back into the transmit clock (TCLK) of a transmitter? Typically, this type of setup is only good for 1-2 hops. Applications using more than two hops will require a filter on RCLK to clean up the jitter. A FPGA will also need to ensure that setup and hold times are being met. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 Do I need to use the REFCLK on LVDS receivers? Yes. The receiver uses REFCLK to strobe the incoming data and to recover the clock. Please note that there is no phase relation between REFCLK, TCLK, or RCLK. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 For transmitters and receivers with an embedded clock, why does a recovered clock (RCLK) signal appear after data is no longer being sent to the transmitter inputs? When active data is removed from the transmitter''s inputs, the transmitter will continue to send at minimum, a clock bit. The receiver continues to track this clock bit and recovers this as RCLK. To completely disable the transmitter’s output, the transmitter powerdown pin or output enable pin should be used. If the powerdown or output enable pin is used, the receiver will need to resynchronize to the transmitter. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 What is a repetitive multi-transition (RMT) pattern? Patterns where more than one Low-High transition takes place in a clock cycle over multiple cycles is called a RMT pattern. This occurs when any bit, except bits such as DIN9 (for the 10-bit embedded clock SerDes), is held at a low state and the adjacent bit is held high, creating a 0-1 transition. This could prevent a LVDS receiver from locking or cause it to lock to the fixed 0-1 data bit instead of the actual embedded clock bit. Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 What type of probes should be used to probe LVDS signals? Always use high-impedance (1M), low capacitance (<1pF) probes with adequate bandwidth to probe LVDS signals. Tektronix and Agilent both make differential probes that are high impedance and low capacitance Relevant Part: DS92LV1021;DS92LV1021A;DS92LV1224;DS92LV1023;DS92LV1212A;DS92LV8028;SCAN928028;DS92LV1260;SCAN926260;SCAN921023;SCAN921224;SCAN921025;SCAN921226;SCAN921260;SCAN928028;DS92LV16;DS92LV18;DS92UT16 What''s the maximum output frequency of the DS92LV1021? Since the DS92LV1021 has a max. data rate of 480 MBit/s (including the clock information) the maximum frequency output is 1/2 that; 240 MHz. Even though data and clock are serialized, there is enough clock information for the DS92LV1210 to clock in each bit so the frequency is 1/2 the data rate (synchronous data), not equal to the data rate, as with asynchronous data Relevant Part: DS92LV1021 The max data rate for the DS92LV1021 is sometimes quoted as 480 Mbp/s and sometimes as 400 MBit/s; what is the real max data rate? Both numbers are correct: the DS92LV1021 embeds 2 additional bits to the 10 data bits as clock information therefore transmitting 12*40MHz = 480 MBit/s. However, since only 10 of the bits are actually data, the "payload" or information rate for each cycle is 10*40MHz = 400 MBit/s. The device is 83% (10/12) efficient Relevant Part: DS92LV1021 What is the frequency of the DS92LV1210 REFCLK input? The REFCLK input of the DS92LV1210 should be operated at the same nominal frequency as the TCLK input of the DS92LV1021. For example, if data is being clocked in to the DS92LV1021 at 40 MHz the DS92LV1210 REFCLK should also be 40 MHz. There is no phase requirement between REFCLK and TCLK Relevant Part: DS92LV1210;DS92LV1021 What''s a SYNC pattern? A SYNC pattern is a special pattern of ones and zeroes output by the DS92LV1021 to enable the DS92LV1210 to phase lock to the rising edge of the embedded clock. In actuality, it is simply 6 ones followed by 6 zeroes. SYNC patterns are automatically output by the 1021, regardless of the data at the DINO-DIN9 inputs, when either the SYNC1 or SYNC2 input is held high Relevant Part: DS92LV1210;DS92LV1021 What''s the purpose of the REFCLK input on the DS92LV1210? The DS92LV1210 REFCLK input serves 2 purposes. First, it is used as a time reference for the clock recovery section. The Deserializer PLL initially locks to this clock and then to the data stream. Second, REFCLK is used to run the internal state machine, which indicates the status (/LOCK, PWRDWN, REN) through the DS92LV1210 Relevant Part: DS92LV1210 How well does the DS92LV18 perform in cable drive applications? The DS92LV18 can be used in cable drive applications with limited capability. If employed to transmit data across a generic category 5 cable, it can operate at its highest operating frequency (66 MHz) with cable lengths up to 10 ft. To transmit the data across longer links, cables with lower nominal attenuation are required. The Belden 89207 20 AWG twin-ax cable has proven to be a solid performer. At 66 MHz operation (1.32 Gbps data rate), the DS92LV18 can drive the Belden 89207 cable up to 20 ft. Careful interconnect design should be implemented to maximize the cable drive capabilities of the DS92LV18. Selecting controlled impedance cables and connectors greatly enhances the chance for an error-free data transfer. Relevant Part: DS92LV18 Why was the DS92LV18 LVDS Ser-Des designed to send an 18-bit payload, rather than the typical 8 or 16 bits? Although data buses are often byte-oriented, many systems need to send extra information along with the data. Designers can use the extra bits of the DS92LV18 to conveniently send this extra information at the base data bus clock rate. As an example, a 8-bit/10-bit solution would require additional logic and buffering, twice the clocking rate (to accommodate the extra bytes), and a mechanism to add/drop comma (for synchronization) and idle characters (for rate adaptation). These features, and more, are built-in to the DS92LV18, simplifying the system design. In fact, some designers often take advantage of the two extra bits and use them for parity, flag, or control bits where only 16-bits of data transfer are required. Also, the DS92LV18 offers two extra bits, but the same package with the same pinout as its 16-bit counterpart, the DS92LV16. Relevant Part: DS92LV18 Do I need AC-coupling for the equalizer I/O? And if so, what value AC-coupling capacitors should I use? Whether you''ll need AC-coupling really depends on the complimenting SerDes interface. If the signal interfacing with the equalizer I/O has different input thresholds, OR if the SerDes interfacing with the equalizer has a different ground potential, then AC-coupling will be required. The most common and simplest method of AC-coupling is to use a DC-blocking capacitor. The smallest available package should be used, as it will help minimize package parasitics. The value of the AC-coupling cap should be 0.1µF or 0.01µF. Relevant Part: EQ50F100 Do I need a termination resistor on the equalizer CML I/O? The EQ50F100 has internal CML terminations on both the input and output stages. The input stage (IN+/-) of the EQ50F100 is internally terminated with a 100ohm differential load, while internal 50ohm resistors connected from OUT+ and OUT- to VDD terminates the equalizer CML output. Relevant Part: EQ50F100 What is the advantage of a fixed equalizer verses an adaptive equalizer? The EQ50F100 fixed equalizer requires NO adjustment and is code independent. This eliminates the possibility of causing system errors and functions equally well for short-run data lengths, 8b/10b encoded data, or scrambled signals. The EQ50F100 also provides better system noise response due to lower insertion loss. Relevant Part: EQ50F100 What is the maximum speed and channel length the EQ50F100 can equalize on legacy backplanes using FR-4 material? The EQ50F100 equalizes signals up to 6.25Gbps. At 6.25Gbps, the longest legacy backplane built with FR-4 material can equalize approximately 10-inches. At 5Gbps, the EQ50F100 can equalize up to 16-inches of legacy backplane trace length using standard FR4 material. Relevant Part: EQ50F100 Why should I use a stand-alone backplane equalizer? A stand-alone backplane equalizer, such as the EQ50F100, provides placement and routing flexibility. It also enables cost effective system upgrades by increasing data rates on legacy FR-4 backplane from 1.25Gbps to 6.25Gbps. Relevant Part: EQ50F100 Do I need AC-coupling for the equalizer I/O? And if so, what value AC-coupling capacitors should I use? Whether you''ll need AC-coupling really depends on the complimenting SerDes interface. If the signal interfacing with the equalizer I/O has different input thresholds, OR if the SerDes interfacing with the equalizer has a different ground potential, then AC-coupling will be required. The most common and simplest method of AC-coupling is to use a DC-blocking capacitor. The smallest available package should be used, as it will help minimize package parasitics. The value of the AC-coupling cap should be 0.1µF or 0.01µF. Relevant Part: EQ50F100 Do I need a termination resistor on the equalizer CML I/O? The EQ50F100 has internal CML terminations on both the input and output stages. The input stage (IN+/-) of the EQ50F100 is internally terminated with a 100 ohm differential load, while internal 50 ohm resistors connected from OUT+ and OUT- to VDD terminates the equalizer CML output. Relevant Part: EQ50F100 What is the advantage of a fixed equalizer verses an adaptive equalizer? The EQ50F100 fixed equalizer requires NO adjustment and is code independent. This eliminates the possibility of causing system errors and functions equally well for short-run data lengths, 8b/10b encoded data, or scrambled signals. The EQ50F100 also provides better system noise response due to lower insertion loss. Relevant Part: EQ50F100 What is the maximum speed and channel length the EQ50F100 can equalize on legacy backplanes using FR-4 material? The EQ50F100 equalizes signals up to 6.25Gbps. At 6.25Gbps, the longest legacy backplane built with FR-4 material can equalize approximately 10-inches. At 5Gbps, the EQ50F100 can equalize up to 16-inches of legacy backplane trace length using standard FR4 material. Relevant Part: EQ50F100 Why do I need a stand-alone backplane equalizer? A stand-alone backplane equalizer, such as the EQ50F100, provides placement and routing flexibility. It also enables cost effective system upgrades by increasing data rates on legacy FR-4 backplane from 1.25Gbps to 6.25Gbps. Relevant Part: EQ50F100 How do I terminate an unused output on the LMH0030? Every coaxial cable driver in an SDV system, regardless of type, is terminated to ground in 75Ω at the receiver input (far end of cable). Both ends of that coaxial cable link are AC (capacitively) coupled. In operation and to preserve driver balance, both outputs of a differential driver must be equally loaded and terminated. So, a differential driver is never actually operated in an unbalanced load condition. Though only one output is connected to a coax cable and receiver, the other output is dummy loaded in virtually the same network minus the cable. When using a differential driver in a single-ended application, load the unemployed output to ground after the coupling capacitor with a termination resistor of the same value as that used to terminate the employed output at the receiver input (end of the cable). The LMH0030 data sheet test circuit shows the normal required output interface without the cable and its termination to ground. Relevant Part: LMH0030;CLC001;CLC005;CLC006;CLC007;CLC001;CLC020;CLC021 Can I use LVDS components in Fiber applications? Yes. We recommend all of our serializer and deserializer parts for use with fiber or AC-coupling as long as the customer guarantees they have enough transitions to keep the DC offset balanced. For example, customers can use 8b/10b coding with the 10-bit serializer and deserializer parts to keep the DC balance, or they can use a scrambling technique such as that used in the Utopia Bridge or Packet Bridge products. Relevant Part: LVDS When designing components into board level applications, do I need to use bypass capacitors? Yes. No matter how simple the design, bypass capacitors are always recommended. Please see product datasheets for bypassing suggestions. Relevant Part: LVDS Can I AC-couple LVDS parts? Yes. However, when AC-coupling LVDS signals, the common-mode voltage component of the signal is lost. A voltage biasing resistor network may be required for some receivers to work properly. Optimal performance of AC-coupled LVDS signals will require some type of data encoding to keep the DC-offset balanced. Relevant Part: LVDS Can I AC-couple LVDS parts? Yes. However, when AC-coupling LVDS signals, the common-mode voltage component of the signal is lost. A voltage biasing resistor network may be required for some receivers to work properly. Optimal performance of AC-coupled LVDS signals will require some type of data encoding to keep the DC-offset balanced Relevant Part: LVDS Can I daisy-chain LVDS parts by connecting the recovered clock (RCLK) of a receiver back into the transmit clock (TCLK) of a transmitter? Typically, this type of setup is only good for 1-2 hops. Applications using more than two hops will require a filter on RCLK to clean up the jitter. A FPGA will also need to ensure that setup and hold times are being met. Relevant Part: LVDS Can I hot-plug LVDS devices? Yes. We guarantee hot-plug insertion support for all of our receiver and transceiver products. Typically, this feature is not recommended for transmitters. The correct contact order for hot-plugging devices should be ground, power, and then I/O''s. Relevant Part: LVDS I want to probe LVDS signals but am not sure what type of probes I should use. Always use high-impedance (>1M Ω ), low capacitance (<1pF) probes with adequate bandwidth to probe LVDS signals. Tektronix and Agilent both make differential probes that are high impedance and low capacitance. Relevant Part: LVDS Can LVDS devices only be connected through backplanes? No. LVDS signaling can also be transmitted through different types of cables. Even low-cost CAT5 cables can be used with reliable performance. Relevant Part: LVDS I want to use CAT5 cable as an interconnect, but the data rates advertised by your parts seem to be faster than what CAT5 cable is rated for. LVDS signaling works well on CAT5 and many other types of cables. A properly designed links with the appropriate drivers and receivers can achieve 2.0 Gbps over CAT5 cable. Relevant Part: LVDS For transmitters and receivers with an embedded clock, I stop sending data to the transmitter''s inputs, but I still get a recovered clock (RCLK) from the receiver. When active data is removed from the transmitter''s inputs, the transmitter will continue to send, at minimum, a clock bit. The receiver continues to track this clock bit and recovers this as RCLK. To disable the RCLK output when data is not present at the transmitter''s inputs, the user can utilize the transmitter powerdown pin or output enable pin. Alternatively, the receiver''s powerdown pin, or output enable pin, may also be used to disable the RCLK output. Note: if the receiver powerdown pin is used, the receiver will need to resynchronize to the transmitter after exiting powerdown mode Relevant Part: LVDS What are the general PCB design recommendations for National Semiconductor''s Interface Devices? a) Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals. Dedicating planes for VCC and Ground are typically required for high-speed design. A solid ground plane is required to establish a controlled (known) impedance for the transmission line interconnects. Narrow spacing between power and ground planes will also create an excellent high frequency bypass capacitance. b) Isolate fast edge rate CMOS/TTL signals from LVDS signals, or they may couple crosstalk onto the LVDS lines. It is best to put TTL and LVDS signals on a different layer(s) which should be isolated by the power and ground planes. c) Keep drivers and receivers as close to the (LVDS port side) connectors as possible. This helps to ensure that the differential lines do not pick up noise generated from the board, which can result in higher EMI. This recommendation also helps to minimize skew between the lines. d) Bypass each LVDS device and also use distributed bulk capacitance. Surface mount capacitors placed close to power and ground pins work best. e) Power and ground traces should be wide (low impedance) traces. Do not use 50 Ω design rules for power and ground traces. Their function is to be a low impedance path. f) Keep ground PCB return paths short and wide. Provide paths that create the smallest return loop for image currents. g) Systems connected through cables should provide a common ground wire between the systems. This provides a short known path for common-mode currents to return. h) Use two vias to connect bypass capacitor pads to power and ground planes. This minimizes inductance effects. Surface mount capacitors are recommended since they are compact and can be located close to device pins. What is the major difference between DS92LV1210 and DS92LV1212? The DS92LV1210 needed a SYNC pattern in order to get locked. The DS92LV1212 can lock to random data as long as the data is not a repetitive multi-transition Describe RMT and how it effects the device. RMT - repetitive multi-transition- is a specific repeated pattern. For our device, RMT occurs when there is more than one low-high transition between clock bits. The part expects to see only one permanent low-high transition and this would be CLK0-CLK1. Any time any of the bits (except Bit 9) are held low and the next adjacent bit is held high, RMT will occur. For example, B0 held low and B1 held high will create an additional low to high transition-RMT. So in an application, you need to ensure that the bits are not hard tied low/high in this manner What is LVDS? LVDS is short for "Low Voltage Differential Signaling" and is a high speed, low power data transmission standard. For more information, see our LVDS Featured Community. Does REFCLK need to be running at all times? We recommend that REFCLK remain running at all times. This is because the REFCLK runs the internal state machine. When the Deserializer shifts lock from REFCLK to embedded clock, then REFCLK can be taken away and the part may still work. However, should the Deserializer lose lock, without the presence of REFCLK, the LOCK pin will remain low incorrectly, indicating a locked part. Since, REFCLK runs the state machine, without REFCLK the device''s lock loss (/LOCK=1) can''t be indicated How close does the REFCLK frequency have to be to the TCLK frequency? REFCLK frequency should fall within the following range: 0.97Tclk Is LVDS for point-to-point applications only? No. Multi-point applications are supported with certain Bus LVDS (BLVDS) devices and also with M-LVDS devices, while standard LVDS parts support point-to-point and multi-drop applications. Multi-point LVDS is defined in the new TIA/EIA-899 Standard What is the common mode range for LVDS devices? The common-mode range is +/-1V around the driver offset voltage (+1.25V typical). This supports the input operating range of GND to +2.4V on the receivers. Always use a balanced media and closely-coupled traces to obtain the maximum common mode rejection. M-LVDS supports a typically common mode of +/- 2V How far can LVDS go? LVDS is a short haul interface, envisioned to drive interconnects of a few inches to 10s of meters. Once again, this is application specific, depending upon the LVDS device employed and the required signal quality How much noise margin does LVDS provide? This is related to the +/-1V common mode range of LVDS. Since noise will be coupled as common-mode, the receivers will reject it. LVDS provides more than twice the noise margin of reduced swing single-ended technologies (BTL and GTL+) Is LVDS low noise? YES. Noise generation is minimized in a number of ways. The signal swing is only 300mV, and also a true balanced differential data transmission scheme, and the current mode driver all limit noise generation Is LVDS low Power? Yes, power dissipation is minimized in a number of ways. This includes the CMOS process, the current mode driver design, and also the small load current Does LVDS require a termination resistor? Yes, for two reasons. Since the drivers are current mode, the resistor is required to complete the current loop. Also, since LVDS features sub-nanosecond transition times, the interconnect will be a transmission line, and a termination is required to limit reflections How fast is LVDS? LVDS is envisioned to be forward looking and does not define a maximum data rate within the standard. As maximum data rate is design, technology, and application dependant (required signal quality). Current LVDS parts operate from DC to Giga bits per second range Is there an LVDS standard? Yes, LVDS is standardized in the ANSI/TIA/EIA-644-A electrical characteristics standard titled, "Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits". Revison "A" was completed in 2001. What is defined in the ANSI/TIA/EIA-644-A standard? The LVDS standard is an electrical standard only defining driver output characteristics and receiver input characteristics. Guidelines are also given on bus configuration, cables, and termination. Protocol, connectors, and bus structure are not defined in this standard, as they are application dependent. It is intended that these parameters are specified by the referencing standard What is the timing requirement between TCLK and Data inputs? You should not violate setup, and should hold times at DIN(0-9) and have TCLK jitter <150ps What are typical lock times for the Deserializer? At 40 MHz, typical lock time from PWRDWN is 4.8 us and 4.5us from SYNCPAT Would SYNC and LOCK signals be susceptible to noise on the cable? The SYNC inputs of the Serializer are deglitched by the pulse width requirement of those inputs. In order to be recognized as a "SYNC request" a SYNC input must be held high for at least 4 consecutive TCLK edges. Narrower pulses and glitches are ignored How do you terminate the bus? Point-to-point: single termination at the LVDS serial input. Multi-drop with single termination: When your serializer is in the first slot of your bus, then you only need single termination at the far end of the bus. Multi-drop with double termination: When your serializer is not on the first slot of the bus, you need to use termination at each end of the bus. A 100 Ω differential bus must be terminated at each end with a 100 Ω or less depending on cap load and spacing. But it should not be any less than 54 Ω . The LVDS serial output is rated for a 27Ω load. Can a different value be used? Yes, you can use a different value. You should use whatever resistance matches the line that is being driven. The total RL we use is 27 Ω , this would be two 54 Ω resistors in parallel which represents a heavily loaded backplane. We have recommended 27 Ω because our AC characteristics slightly change with higher resistance. Specifically, rise and fall times could change. Also, keep in mind that with a higher value resistor you will have a higher Vod- differential swing. Can you pull-up /LOCK output? Yes, with a 2K Ω resistor. Can 3.3 volt LVDS drivers be used to drive 5 volt LVDS receivers? Yes When the Deserializer is disabled (REN=0), what happens to your LOCK output? This will tri-state ROUT0-9, RCLK and /Lock. However, the Lock pin will only be in tri-state if the device is locked (/LOCK=0) when REN is disabled. If the Deserializer is not locked when REN is disabled, the /LOCK output will remain high and will go low if the Deserializer locks, regardless of REN Is there a powerup sequence for the Serializer? Yes, upon powerup, the Tx PWRDWN pin needs to be toggled from high to low and back to high again to initialize the part. Another way would be to hold the PWRDWN pin low for 1us to make sure the VCC pins have stabilized What kind of power supply filtering is needed for BusLVDS devices? Bypass each device with 0.1uF/0.01uF/0.001uF capacitors in parallel. You may also want to use a bulk capacitance for each PCB. A 10uF 35V tantalum capacitor can be used Can LVDS drivers drive Bus LVDS receivers Yes Can PECL drive LVDS receivers directly? Usually, LVPECL can drive LVDS directly without level translation circuitry because our LVDS devices operate over a wide common-mode range. However not all LVDS devices operate over a wide common-mode range. In addition LVDS receivers do not usually take standard PECL (as opposed to LVPECL) levels well since their VOS is typically about 3.6V. This is above our common mode operating range. It does work sometimes, but with very poor performance Once the device loses lock, how can the system resynchronize? The system needs to monitor the lock pin. Once the system detects loss of lock (/LOCK=1), then in order to resynchronize the Deserializer, sync patterns need to be transmitted. Transmission can be achieved through the assertion of either the SYNC 1 or SYNC2 pin. The easiest method to detect the lock pin and transmit sync patterns is by feeding back the /Lock output of the deserializer to either of the SYNC pins on the serializer What is important when selecting cables and connectors for LVDS? When choosing cables and connectors for LVDS it is important to remember the following: a) Use controlled impedance media. Choose cables and connectors that have a differential impedance of 100 Ω This should minimize major impedance discontinuities that cause signal reflections. b) Balanced cables (twisted pair) are usually better than unbalanced cables (ribbon cable, multi-conductor) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects. They also tend to pick up electromagnetic radiation as common-mode (not differential-mode) noise, which is rejected by the receiver. c) For cable distances < 0.5m, most cable types can be used effectively. For distances 0.5m < d < 10m, CAT 5 (Category 5) twisted pair cable works well, is readily available, and is relatively inexpensive. Other types of cables may also be used for specific applications. Can REFCLK be removed? No, as in the DS92LV1210 REFCLK runs the internal state machine Can the DS92LV1212 replace the DS92LV1210? Yes you can as long as you don''t have lock time requirements that are faster than the 1212''s capability. Also the 1212 has tighter frequency requirement for REFCLK relative to Tclk Can the devices be daisy chained? We do not recommend daisy chaining. The reason for this is jitter accumulation. The jitter accumulated in the serializer is passed on to the Deserializer. The jitter at the Deserializer output is amplified and it would get passed on to the next serializer. This jitter accumulation will result in lock loss Can you load the /LOCK pin with 2 loads and a cable? Yes you can How close does the REFCLK frequency have to be to the TCLK frequency? REFCLK frequency should fall within the following range: 0.95Tclk How is loss of lock indicated? When the Deserializer loses lock, the lock pin will be asserted high within 4-5 clock cycles. Therefore, the last 5 cycles of data transmitted can be invalid. This should be detected by the protocol Is there a failsafe condition for the Serializer? With floating inputs, all inputs (DINO-9, DEN, PWRDWN, TCLK, TCLK R/F*, SYNC) will be pulled low. This creates a Tri-state condition at the outputs What are some recommended interconnect media for the device? We have successfully utilized the device on a backplane. We have also performed cable testing using UTP CAT 5 cable. However, a variety of media can be used as long as impedances are matched and you limit the number of transitions between media of different Zo to minimize reflections What are the advantages of MLVDS? Stronger drive, slower edge rates, and wider common mode compared to conventional LVDS. MLVDS is capable of supporting up to 32 loads. What are the typical lock times? Typical random data lock times are 570 us at 40MHz. Typical lock time from PWRDWN is 7.4us and 14.4us from SYNCPAT What is the RCLK jitter during operation? We have measured about 600 ps Peak-Peak when running at nominal conditions (40MHz/3.3V/Room Temp) sending random data For the LP2995 DDR Termination Regulator, is a 100uF capacitor required on the output when using a single DDR SRAM? Yes, the 100 uF output capacitor is a minimum value. Additional output capacitance may be required for improved transient response. But the 100 uF is a minimum that must be maintained to insure the stability of the LP2995. For more information, see the "Output Capacitor" discussion in the Component Selection portion of the LP2995 datasheet. Relevant Part: LP2995