Ethernet Should I use right angles (90 degrees) or larger angles (>90 degrees) for TX and RX traces on my PCB layout? Angles >90 degrees are generally a better practice. At the corner of a 90 degree bend, the trace is wider than the rest of the trace (transmission line width increases). This results in a decrease in Zo, the intrinsic impedance of the trace. This impedance mismatch at the corner causes reflections, signal distortion, and noise. At sharp 90 degree corner the electronic fields become concentrated, causing potentially destructive electromagnetic radiation from that point. This could also manifest itself as EMI. Rounded 90 degree corners on these traces work equally well. Relevant Part: DP83815;DP83816;DP83818;DP83846;DP83847;DP83848;DP83865 How can an EEPROM be programmed for use on a DP83815 or DP83816 based design? Programming the EEPROM on a DP83815 or DP83816 based design can be done ''on-board'', during the production phase of an end product. This allows for higher yield and more efficient flow of product manufacturing. The programming can be done using the DIAG utility located on the DP83816 drivers and utilities page. Source code is available for customizing the software. Relevant Part: DP83815;DP83816 What type of clock source should be used with the DP83815 or DP83816? The DP83815 and DP83816 clock can be sourced from a 25 MHz, ± 50 ppm oscillator connected to X1, leaving X2 floating. The clock could also be provided by a 25 MHz, ± 50 ppm, parallel resonance, 20 pF load, < 40W ESR crystal, connected to X1 and X2. When using this crystal load capacitors or approx. 27 pF should also be used. Due to the interaction of the external crystal, load capacitors, internal resonance circuit and PCB traces, the optimal value for the load capacitors should be verified by bench tests and if needed, adjusted slightly. Relevant Part: DP83815;DP83816 How can I program the MAC address into a DP83815 or DP83816? There are 2 methods to program the MAC address into the DP83815 or DP83816. "Static": MAC address is loaded from the EEPROM (at power up or when the EEPROM information is reloaded. "Dynamic": MAC address is loaded directly into the device. Used when the platform does not have an EEPROM. Beware: addresses loaded using method 2 will be lost if the device is reset, powered down, or an EEPROM load is issued. Please refer to Application Note 1351 " MAC Address Programming for DP83816 MacPHYTER-II and DP83815 MacPHYTER" for more information. Relevant Part: DP83815;DP83816 What are the requirements for the DP83815 or DP83816 clock source? The DP83815 and DP83816 devices require a 25 MHz, ± 50 ppm clock source w/ approx 1V amplitude. Relevant Part: DP83815;DP83816 What EEPROM is recommended with the DP83815 or DP83816? The reference designs for the DP83815 and DP83816 use a 2.7V EEPROM, connected to the same 3.3V VDD rail the DP83815 or DP83816 uses. This is to ensure the data is ready from the EEPROM prior to being read by the network chip and used fo rconfiguration. The reference designs use FM93C46L. Relevant Part: DP83815;DP83816 Where can I find datasheet, schematics or Bill of Materials (BOM) for the DP83815 or DP83816 reference design? Please refer to the DP83815 and DP83816 reference design web page. Relevant Part: DP83815;DP83816 Are there any differences in pins functionality between the DP83815 and the DP83816? Please refer to Application Note 1323 for more information. Relevant Part: DP83815;DP83816 How can I update a DP83815 design to a DP83816 design? Please refer to Application Note 1323 for more information. Relevant Part: DP83815;DP83816 What drivers are available for the DP83816 and the DP83815? Please refer to the following link for all drivers available for the DP83816:http://www.national.com/appinfo/networks/macphyter2.html Additionally, please refer to the following link for all drivers available for the DP83815: http://www.national.com/appinfo/networks/0,1804,829,00.html Relevant Part: DP83815;DP83816 Are there any package differences between the DP83816 and the DP83815? The DP83816 exists in the same LQFP package as the DP83815. However, the DP83816 is not available in a LBGA package Relevant Part: DP83815;DP83816 Does the MacPHYTER DP83815 meet the 5V PCI signalling requirements? National does specify that "The DP83815 conforms to 3.3V AC/DC specification, but has 5V tolerant inputs," in section 3.3.1 of the datasheet under PCI System Bus Interface Definitions. There shouldn''t be any issues using the MacPhyter with 5V signalling: If you refer to the PCI local bus specs rev.2.2, in section 4.2.3.2. the timing parameters for 5V and 3.3V signalling are identical. Also if you compare the DC specs for the 5V and 3.3V signalling environments in sections 4.2.1.1 and 4.2.2.1 you will find that the Voh and Vol for 5V signalling fall in the range specified for Vih and Vil for 3.3V signalling respectively Relevant Part: DP83815 What is included in the DP83815-MAAP? The MAAP (MacPhyter Accelerated Adoption Package) kit includes: Demo board, Board documentation, Schematics, Block Diagram, Layout,Gerbers, Bill of Materials, Device documentation, Datasheet, User Information Notes, and Apps. Notes. Software: Drivers: Microsoft WHQL-certified Win 95, Win 98, Win NT and Win CE,Linux and VX Works, C-ODI Server Driver, Installation Files, Support Documentation, Sample Source Code, and Certification (where applicable). For up-to-date information, please visit our Networks Featured Site. Relevant Part: DP83815 How can the auto negotiation function for this MACPHY eval board be turned off? On the MacPHYTER, Autonegotiation is disabled in bit 12 of the Basic Mode Control Register. 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set. 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode. The default value of this bit is dependent on the setting of the ANEG_SEL bits 15:13 in the CFG register, address 0004h, which can be also be set in the EEPROM by writing to register 0003h bits 10:12. Relevant Part: DP83815 Is there a driver that supports multiple PCI bridges on board? With the exception of the DOS drivers (DOS has a tough time with multiple cards), all drivers support multiple cards including multiple PCI-PCI bridges Relevant Part: DP83815 Please list vendors making PCI card using the DP83815. Netgear is shipping two PCI cards that use our DP83815. The two cards are FA311 w/o WOL and FA312 with WOL. Relevant Part: DP83815 Why are 54.9 Ohm termination resistors used for RX+/-, but 49.9 Ohm; used for TX+/-? The internal circuitry of RX+/- has some internal resistance, that in parallel with the 54.9 ohms provides approximately 100 ohms, maintining the impedance seen on the signal path. Relevant Part: DP83816 After I installed a DP83816 family PCI Network Adapter, I received IRQ or resource conflict; what should I do? The Interrupt Request (IRQ) is configured and administered by a system’s Basic Input Output System (BIOS). Shutdown the system, and enter the BIOS and check for PCI configuration, referring back to your motherboard manual, manually reserving an IRQ has sometimes resolved the issue. Another option would be to move the PCI NIC to a different slot. Relevant Part: DP83816 I have downloaded the driver, what should I do now? Read the readme file. In most cases, the readme file is your number one helper. Readme files can be found on the DP83816 drivers/utilities Relevant Part: DP83816 What drivers are available for National Semiconductor DP83816 family PCI Network Adapter? Links to National''s Network datasheets, drivers and utilities can be found on the Networks featured community or the DP83816 drivers page. Relevant Part: DP83816 What is the placement of DP83816, transformer and RJ45? The design should layout that keeps the distance between DP83816 and transformer as short as possible. Likewise, the distance between the transformer and RJ45 should be kept short as well. Relevant Part: DP83816 What kind of performance can I expect from DP83816 family of PCI Network Adapter? We use Chariot ( http://www.NetIQ.com ) for benchmarking out devices and software. The DP83816 family of devices will provide wire speed throughput, assuming the system has sufficient horsepower to drain the device. Throughput in the range of 94-96 Mb/s (each direction) has been achieved with the DP83816. Relevant Part: DP83816 Where should the TX+/- and RX+/- termination resistors be placed? Place the termination circuitry (resistors, capacitors and inductor) close to the DP83816. Placing the termination components close helps improve the return loss. Relevant Part: DP83816 Why should I keep differential signal traces equal length? Differential signal traces should have equal length so that the signal will arrive at the far end at the same time. Thus, there is no common mode noise current flowing. Relevant Part: DP83816 Why should I route differential signal traces close together? The closer the differential pair, the smaller the current loop. The loop is the area encompassed by the signal and its return path. EMI is affected by this characteristic. Relevant Part: DP83816 How can the DP83816 be configured to work in 100Mb/s operation only (forced mode)? For 100Mb HD (Half Duplex): - Set Register offset 04h as such: CFG[15:13] = 010, This value should be programmed into the EEPROM and loaded from it - Set Register offset 24h as such: TXCFG[ 31:30] = 00 - Set Register offset 34h as such: RXCFG[28] = 0 For 100Mb FD (Full Duplex): - Set Register offset 04h as such: CFG[15:13] = 110, This value should be programmed into the EEPROM and loaded from it - Set Register offset 24h as such: TXCFG[31:30] = 11 - Set Register offset 34h as such: RXCFG[28] = 1 Please be aware that when connecting this device (in full duplex forced mode), to a link partner that is set to autonegotiation or in half duplex forced mode, will create operational issues. Relevant Part: DP83816 Is the pull-down on 3Vaux necessary? Could it be left floating? On the DP83816, the 3Vaux pin (pin 122) has an internal pull-down. If the power management function is not used, it is recommended that an external 1KΩ pull-down resistor be used. Relevant Part: DP83816 What are the recommendations for an RJ45 that has 10/100 Ethernet and USB connections integrated? Pulse and Bel both provide acceptable devices for this. Relevant Part: DP83816 Can LANVCC noise cause transmit jitter problems on the DP83816? Yes. Excessive noise on LANVCC can cause problems with jitter. The noise can be reduced by adding a 22µF bypass capacitor. Relevant Part: DP83816 How would a ferrite in the RJ45’s ferrite affect the IEEE 802.3 signals? A ferrite bead in the RJ45 could affect the data signals by making the eye diagram worse. At critical frequencies, return loss is not significantly affected. Relevant Part: DP83816 What is the function of the 0.1uF ceramic capacitors between system GND and chassis GND? The capacitors between system GND and chassis GND provide an AC path to help reduce EMI emissions. Relevant Part: DP83816 What is the purpose of the center tap capacitor on the TX+/- and RX+/- pairs of the DP83816? The combination of the resistors and capacitors on the center tap forms AC common-mode termination path Relevant Part: DP83816 What value capacitor should be used for the center tap connection? The center tap capacitor should be 0.1 µF or 0.01 µF. Relevant Part: DP83816 Does the DP83816 support Flow Control? Yes. If the Pause Control/Status Register (PCR), located at offset 44h, is set up properly (bits 31 and 30 need to be set to enable the Pause function), then a correctly received pause packet will pause transmitting accordingly. However, to transmit pause packets, software intervention is required. National Semiconductor drivers do not currently support this feature Relevant Part: DP83816 How can I install the DP83816 driver for a certain O/S? Please refer to the following DP83816 MAAP user guide for details on driver installation. Relevant Part: DP83816 How can the DP83816 be configured to work in 10Mb/s operation only (forced mode)? For 10Mb HD (Half Duplex): Set Register offset 04h as such: CFG[15:13] = 000, This value should be programmed into the EEPROM and loaded from it Set Register offset 24h as such: TXCFG[31:30] = 00 Set Register offset 34h as such: RXCFG[28] = 0 For 10Mb FD (Full Duplex): Set Register offset 04h as such: CFG[15:13] = 100, This value should be programmed into the EEPROM and loaded from it Set Register offset 24h as such: TXCFG[31:30] = 11 Set Register offset 34h as such: RXCFG[28] = 1 Be aware that when connecting this device (in full duplex forced mode) to a link partner that is set to auto-negotiation or in half duplex mode, will create operational issues. Relevant Part: DP83816 I have a 5V system, can I use the 3.3V DP83816 device? Yes. Since the device has 3.3V signaling with 5V tolerant I/O, this is not a problem. You will need to provide the 3.3V supply power to the device, e.g. 5V fed through 3.3V regulator Relevant Part: DP83816 Where can I find collateral material (datasheet, app notes, schematics) for the DP83816? Please refer to the following web link for Collateral Info:networks.national.com Relevant Part: DP83816 Where can I find more information on Power Management (Sleep and WOL) settings for the DP83816 and how it works? Please refer to sec 6.0 in the DP83816 datasheet Relevant Part: DP83816 What speed does the DP83840A default to during auto negotiation? The DP83840a defaults to 10mb/s when it auto negotiates. It is possible to write to the ANAR during auto negotiate to force the chip into 100mb/s mode Relevant Part: DP83840 Does the Phyter send different output for every different invalid 5bits symbol? No, the Phyter sends one output for all invalid 5bit symbols Relevant Part: DP83843 What fiber optics transceivers are supported by the PHYTER? The Phyter will work with HFBR-5903 and HFBR-5103 HP Fiber Optic Transceivers. Relevant Part: DP83843 Is there a list of qualified magnetic components for the DsPhyter? We used Pulse Engineering part #PE68515 on our evaluation board, However, any magnetic that meets the IEEE spec should work. Relevant Part: DP83846AVHG What is the power dissipation for the DsPhyter (DP83846)? The max power dissipation rating for the DsPhyter is 200mA X 3.6V = 0.720 Watts Relevant Part: DP83846AVHG What type of transformer should I use with DsPHYTER? To date, the only magnetic tested on the DsPHYTER is the Pulse Engineering PE-68515. There should not be any problems with any of the established magnetics vendors. There are also integrated Magnetics/RJ45 packages available from Amphenol, and InNet. Relevant Part: DP83846AVHG What transformers are recommended to be used with the DP83847 and DP83848? Following is a list of manufacturer''s transformers, compatible with the DP83847: Pulse Relevant Part: DP83847;DP83848 Do you have any reference designs for DP83847 part? Yes, there are reference designs for DsPHYTER II. The 10/100 Ethernet MAU schematic is currently available on National''s Network''s site. The 10/100 Ethernet ACR card schematic is available upon request. Relevant Part: DP83847 Do you have information on how to layout the DP83847 device? The 56-LLP Package Gerber file can be download from the packaging site. Relevant Part: DP83847 I am planning to use the DP83847, and would like to know more about the packaging for this device. Is there any information available? The DP83847 comes in a 56-LLP. Application Note #1187 "Leadless Leadframe Package (LLP)" provides more information on this package . Relevant Part: DP83847 How do I know the DP83847 device is alive when it is not connected? To verify the DP83847 is alive, while not connected to a network, check for outputs at these pins: RBIAS pin (3): 1.2V C1 pin (42): approx. 1.8V TXC pin (36): clock present Voltage presence indicates adequate power applied to the device. Depending on the configuration, the MII TXC pin has an output frequency of 25 MHz (100Mb/s) or 2.5 MHz (10Mb/s). Relevant Part: DP83847 Is it required that the GND bars (58, 60, 62, 64) be soldered down? Will there be any adverse thermal effects on the part by doing this? Since the GND bars (58, 60, 62, 64) are internally connected to the ground pad (65), it is not required that they be soldered down. There will be no adverse performance of the device. Similarly, there will be no adverse thermal impact to the device. However, it is still recommended to follow the instructions in the 56-LLP Application Note # 1187 for maximum performance stability. Relevant Part: DP83847 What are the differences between an MII and SS-SMII connection? MII is defined in the IEEE 802.3u standard. SMII is defined in by SMII Specification 2.1 (Cisco). Some basic differences include: MII - 25 MHz clock, 18 control pins, SMII - 125 MHz clock, less control pins, 4 new signals. Relevant Part: DP83847 What are the oscillator or crystal requirements for the DP83847? All parts should be thoroughly tested and validated by the customer before using them in production. The requirements for the clock inputs for DP83847 are: 25 MHz Oscillator Requirements: Frequency: Typical 25 MHz, Tolerance ±50ppm Frequency Stability: Max ±50ppm, 0 to 70° C, 1 year aging, load change Rise/Fall Time: Max 6 ns, 20 to 80% Jitter (short term): Max 25 ps, Cycle to cycle, driving 10 pF load Jitter (long term): Max 200 ps, Accumulative over 10 µs Symmetry: Min 40% and Max 60% 25 MHz Crystal Requirements: Frequency: Typical 25 MHz, Tolerance ±50ppm Frequency Stability: Max ±50ppm, 0 to 70° C, 1 year aging, load change Load Capacitance: Min 15 pF and Max 40 pF Recommended standard type: HC49 or HC49-US (thru holes) Manufacturers: Vite Technology www.viteonline.com Saronix www.saronix.com Crystal type: HC49 Valpey Fisher www.valpeyfisher.com TXC www.txc.com.tw Relevant Part: DP83847 What is significant about pin 44 of the DP83847? Pin 44 is used for internal testing. It is Internal Voltage Regulator Enable. If connection is desired, a General Purpose I/O (GPIO) line with a zero ohm resistor, in series (not populated), is recommended to connect to this pin. Relevant Part: DP83847 What is the RBIAS pin on the DP83847? Can I use a different resistor value with the tolerance of 5%? The DP83847 is designed to work with the calculated resistor value of 10kΩ (1%) . Changing the resistor value or tolerance will affect the functionality of the device. Relevant Part: DP83847 What is the main purpose of having VDD bars (57, 59, 61, 63) soldered down? All VDD bars (57, 59, 61, 63) need to be soldered down for robust performance. Relevant Part: DP83847 What qualification tests have been performed on this part? The DP83847 and its LLP package have passed the Corporate Standard Reliability Test. In addition, the device has also been sent to a third party for further evaluation; specifically this part has been evaluated by the University of New Hampshire (UNH). Relevant Part: DP83847 Why does the link remain at the previous media speed after I set ANAR (Auto-Negotiation Advertisement Register) to a new value? The contents of the ANAR are read into the transmitted Auto-Negotiation link code word upon a power-up, reset or re-start of Auto-Negotiation. To restart Auto-Negotiation, set bit 9 of BMCR (Basic Mode Configuration Register). Relevant Part: DP83848;DP83816;DP83865;DP83847 Why is the termination of the DP83848 RX +/- pair different than the termination of previous National devices? Auto-MDIX operation with the PHYTER family of products requires the same termination to be used on the RX+/- and TX+/- I/O structures. Termination for each MDI pin, TX+, TX-, RX+ and RX- now requires a 49.9 Ω resistor tied to Vdd. Relevant Part: DP83848 What is Auto-MDIX? Ethernet and Fast Ethernet achieve Full-Duplex operation by utilizing 2 sets of differential pairs on the MDI (Media Dependant Interface), each running in Half-Duplex mode. Pins 1 and 2 are used for transmission and pins 3 and 6 for reception by a node''s Physical Layer device. For a hub (defined as either a switch or repeater) the directions are swapped 1 and 2 are receive and 3 and 6 are transmit. This allows any standard node to connect to any hub. To connect one node to another node, or one hub to another hub, the pairs need to be switched, or crossed over. Many hubs provide a special port connection that does the cross-over internal to the box, hence the name MDIX. Auto-MDIX allows the Physical Layer device to automatically detect the orientation of the MID pairs and appropriately configure itself, with respect to the transmit and receive pairs. This removes the limitation of straight-through vs. cross-over cable connection decision, since each pair is equally capable of traffic in either direction. Relevant Part: DP83848 Can one of the standard ports of the DP83858 repeater be used to feed a port of another DP83858 in order to form a 14 port hub function? The two chips would reside on seperate CCAs. Can we use this scheme instead of using the Inter-repeater bus? If not why? The answer to this question is: it depends. If you are talking about Class I repeaters, in the 100Mbps domain, then you are allowed to have only one repeater between any two DTEs (Nodes). In Class II repeaters, you may use a maximum of two repeaters between any two DTEs, however using this scheme you need to be super careful about the timing/bit budget with respect to the packets going in one port of first repeater and coming out of a port on the second repeater. This timing also includes the delay paths through the physical layer. This timing is quite tight and depending on the PHY and Transceiver used for the physical layer, your system can go out of spec easily Relevant Part: DP83858 What are the major differences between 100Base-TX and 1000Base-T? Data rate for 100Base-TX is 100 Mb/s, for 1000Base-T it is 1000 Mb/s. 100Base-TX uses two separate pairs to transmit and receive data, 1000Base-T uses four pairs, each pair yielding 250 Mb/s. 100Base-TX uses MLT-3 signaling , 1000Base-T uses PAM-5 coding. National''s Gigabit PHY also provides extensive signal processing, inc. echo cancellation, equalization, gain compensation, baseline wander compensation, etc. The MAC interface for 100Base-TX uses MII, 4-bit transmit, 4-bit receive, running at 25 MHz. 1000Base-T uses GMII, 8-bit transmit, 8-bit receive, running at 125 MHz. Relevant Part: DP83865;DP83847;DP83848 Why should one upgrade to Gigabit Ethernet? Gigabit Ethernet is a natural progression of the existing 10/100 Mb/s Ethernet cabling infrastructure. Aggregated switch connections may be congesting 10/100 Mb/s Ethernet/Fast Ethernet networks. Gigabit (1000 Mb/s) provides a 10x bandwidth improvement. Gigabit Ethernet is ideally suited for applications such as Network Attached Storage (NAS) and server farms. Relevant Part: DP83865 What is the maximum cable reach for the DP83865? The IEEE 1000Base-T standard requires cabling distances of up to 100m, with a guaranteed bit error rate (BER) of 10-10 .National''s Gigabit PHY has performance better than the IEEE specification to allow for additional length, such as patch cables in the network closet and on the work station end connections. Relevant Part: DP83865 What is National Semiconductor''s Gigabit PHY advantage? National Semiconductor provides a 5th generation, full featured Physical Layer transceiver that support 10Base-T, 100Base-TX and 1000Base-T. The device is an ultra-low power (1.1W), 128-pin PQFP (small outline SMT) package , allowing low cost, space saving system implementation. Relevant Part: DP83865 What is the cable requirement for Gigabit Ethernet over copper? Category-5 (CAT-5) twisted pair cable is required for the Fast Ethernet 100Base-TX technology. Gigabit Ethernet, 1000Base-T, is able to use the same CAT-5 cabling, making it highly cost-effective. The CAT-5 standard is governed by TSB95 and TIA-568-A. To improve the data transmission reliability for Gigabit operation, CAT-5 enhanced (CAT-5e) added headroom on the cabling parameters. Newer standards for cabling, such as CAT-6 and CAT-7 standards, are also emerging. These standards further tighten the specification on the return loss, attenuation, attenuation to crossstalk ratio, near end crosstalk (NEXT), far end crosstalk (FEXT), and impedance for the 100 MHz bandwidth. Relevant Part: DP83865 What is the advantage of Gigabit Ethernet over copper vs optical fiber? Existing Ethernet networks are 98% Category-5 cabling. National Semiconductor''s Gigabit Ethernet products provide a 10x network bandwidth improvement over these existing 10/100 Mb/s networks, using the already installed cabling, avoiding costly fiber optic installations. National Semiconductor''s Gigabit Ethernet products are also interoperable w/ existing 10 Mb/s Ethernet, and 100 Mb/s Fast Ethernet networks, allowing seamless network upgrades. Relevant Part: DP83865 What are the reasons why one should upgrade to Gigabit Ethernet? Below is a list of why one shoudl upgrade to Gigabit Ethernet. New installations should be done using Gigabit Ethernet due to the diminishing cost difference between Fast Ethernet and Gigabit Ethernet. To relieve network bandwidth bottlenecks, the aggregated connection on IP switches connected to servers and uplinks should be Gigabit Ethernet. In the case of server farms, the upgrade to Gigabit Ethernet can be seamlessly accomplished by replacing the Fast Ethernet NIC with a Gigabit Ethernet NIC. To improve work efficiency, users of desktop computers and workstations, need fast connections to servers. There is no training cost involved, as the IT staff i already familiar with the Ethernet standards. The migration is seamless, since there is no rewiring required, and the performance improvement is remarkable (10x). Relevant Part: DP83865 If I have a lower grade cable, can I still use the DP83865 Gigabit Ethernet PHY? Yes. Some older infrastructures use 10Base-T technology, with CAT-3 cabling, the DP83865 can interoperate with this legacy technology without changing the cabling. If the existing network uses 100Base-TX , AT-5 cabling, it is highly recommended to test the cabling and re-certify with a tester conforming to the Level IIe requirements specified in the TIA TSB95 standard. CAT-5e is specified to 100 MHz with added headroom for 1000Base-T operation that is not in the original CAT-5 standard. In the case where existing CAT-5 cabling does not meet the CAT-5e parameters, the National DP83865 can still operate in Gigabit mode. However, 100 m cable reach is not guaranteed. If the installed cabling does not meet CAT-5e grade, 100Base-TX Fast Ethernet mode can be used to operate beyond 100 m cable lengths. Relevant Part: DP83865 What collateral material is available for the DP83865? On the DP83865 reference design webpage, National Semiconductor provides: Datasheet Design Notes Application Notes PCI demo board (NIC), using DP83865 Schematic diagram and Bill of Material (BoM) PCB layout files Software drivers Relevant Part: DP83865 In trying to access the DP83865 registers through MDIO, and I got invalid data. How can this be corrected? There are a number of items that should be checked. Make sure the MDC frequency is not greater than 2.5 MHz. Check if the MDIO data line has a 2K pull up resistor and the line is idling high. Verify the data timing against the datasheet. Make sure the turn around time (TA) is at least 1 bit long. Relevant Part: DP83865 What happens to the TX_CLK and RX_CLK during Auto-Negotiation and during idles? During Auto-Negotiation, the Gig PHYTER V drives a 25 MHz clock on the TX_CLK and RX_CLK lines. After a valid link is established, and during idle time, these lines are driven by 2.5 MHz in 10 Mbps, and 25 MHz in 100 Mbps mode. In 1000 Mbps mode, only RX_CLK is driven at 125 MHz during idles Relevant Part: DP83865 What is the difference between TX_CLK, TX_TCLK, and GTX_CLK? All 3 clocks above are related to transmitting data. However, their functions are different: TX_CLK: The TX_CLK is an output of the PHY and is part of the MII interface as described in the IEEE 802.3u specification, Clause 28. This is used for 10/100 Mbps transmit activity and has two separate functions: 1) It is used to synchronize the data sent by the MAC and to latch this data into the PHY. 2) It is used to clock transmit data on the twisted pair. GTX_CLK: The GTX_CLK is an output of the MAC and is part of the GMII interface as described in the IEEE 802.3z specification, Clause 35. This is used for 1000 Mbps transmit activity. It has only one function: It is used to synchronize the data sent by the MAC and to latch this data into the PHY. The GTX_CLK is NOT used to transmit data on the twisted pair wire. For 1000 Mbps operation, the Master PHY uses the internal 125 MHz clock generated from the CLOCK_IN clock to transmit data on the wire, while the Slave PHY uses the clock recovered from the link partner''s transmission as the transmit clock for all four pairs. TX_TCLK: The TX_TCLK is an output of the PHY and can be enabled to come out on pin 6 (during Test Mode 2 and 3 it is automatically enabled). This is a requirement of the IEEE 802.3ab specification, Clause 40.6.1.2.5. This is used for 1000 Mbps transmit activity. It has only one function: It is used in “Test Modes 2 & 3” to measure jitter in the data transmitted on the wire. The transmitted clock is either the reference clock or the clock recovered from received data is used for transmitting data depending on whether the PHY is in MASTER or SLAVE mode, respectively. TX_TCLK represents the actual clock being used to transmit data. Relevant Part: DP83865 How do I quickly determine the quality of the link over the cable for the DP83865? Idle error indicates either that the cable length is beyond the specified limit or the cable plant does not meet the EIA 568 Category V requirements. The Activity LED indicates the occurrence of idle error or packet activity. You may monitor the quality of the link by viewing the Activity LED during idle Relevant Part: DP83865 What determines Master/Slave mode when Auto-Negotiation is disabled in 1000Base-T mode? Disabling 1000 Base-T Auto-Negotiation forces the PHY to operate in Master or Slave mode. The selection is through MULTI_EN pin. Since there is no way of knowing in advance what mode the link partner is operating, there could be conflict if both PHY devices are operating in Master or both in Slave mode. It is recommended that under normal operation, AN_EN be enabled Relevant Part: DP83865 How long does Auto-Negotiation typically take for the DP83865? Linking in 10/100 Mbps modes is almost instantaneous. In 1000BASE-T mode, two PHY''s typically complete Auto-Negotiation and establish 1000 Mbps operation in less than 5 seconds. The 1000BASE-T Auto-Negotiation process takes longer than the 10/100 Mbps, because gigabit negotiation does Next Page exchanges and extensive line adaptation Relevant Part: DP83865 Why doesn''t the Gig PHYTER V complete Auto-Negotiation if the link partner is a forced 1000 Mbps PHY? IEEE specifications define "parallel detection" for 10/100 Mbps operation only. Parallel detection is the name given to the Auto-Negotiation process where one of the link partners is Auto-Negotiating while the other is in forced 10 or 100 Mbps mode. In this case, it is expected that the Auto-Negotiating PHY will establish a half-duplex link at the forced speed of the link partner. However, for 1000 Mbps operation this parallel detection mechanism is not defined. Instead, any 1000BASE-T PHY can establish 1000 Mbps operation with a link partner in the following two cases: When both PHYs are Auto-Negotiating. When both PHYs are forced 1000 Mbps. Note that one of the PHY''s is manually configured as MASTER and the other is manually configured as SLAVE. Relevant Part: DP83865 What are some other applicable documents for the DP83865? The DP83865 Design Resources page includes link to the following: DP83865 datasheet, which includes design notes, layout notes, and component selection. DP83865 Reference Designs (Schematics, BOM, Gerber files.) AN-1301: Application note on DP83865 and DP83847 sharing the same foot print. AN-1263: Application notes on DP83865 firmware download. and more! You may also be interested in looking at these IEEE resources: IEEE 802.3z “MAC Parameters, Physical Layer, Repeater and Management Parameters for 1000 Mbps Operation.” IEEE 802.3ab “Physical layer specification for 1000 Mbps operation on four pairs of category 5 or better balanced twisted pair cable (1000BASE-T)“. IEEE 802.3 and 802.3u (For 10/100 Mbps operation.) Relevant Part: DP83865 How do I measure fast link pulses (FLP)? In order measure FLPs Auto MDIX function must be disabled. When in Auto MDIX mode the DP83865 outputs link pulses every 150 ms. Note that MDIX pulse should not be confused with the FLP pulses which occur every 125 ms +/- 14 ms. To disable Auto MDIX, AUX_CTL 0x12.15 = 0. Once Auto MDIX is disabled register bit 0x12.14 specifies MDIX mode. ''1'' for MDIX crossover mode and ''0'' for straight mode. In crossover mode, the FLP appears on pins 3-6 of RJ-45 and in straight mode, the FLP appears on pins 1-2 Relevant Part: DP83865 Does National Semiconductor perform any interoperability test on the DP83865? Yes. Before releasing to production, the device is tested in the National Lab with NIC cards, IP switches, and Ethernet hubs from different vendors for interoperability. The device is also tested with CAT5 cables from different manufacturers. Upon passing the National tests, the device is then tested at the Interoperability Lab at University of New Hampshire (IOL-UNH). An IOL-UNH test brief is available from your local sales rep Relevant Part: DP83865 Why can the DP83865 PHY establish a valid link, but cannot transmit or receive data? The PHY is a self-contained device. The PHY can establish link by itself without any MAC or management involvement. Here are some suggestions to isolate the problem. Use the MDIO management access to configure the BIST registers to transmit packets. If the link partner can receive data, the problem may lie in the MAC interface. Check the MAC transmit timing against the PHY datasheet. Verify the receive timing of the MAC device to see if it matches the PHY datasheet. If the PHY receives the data correctly, the activity LED should turn on. Start the debugging at the slower 10 Mbps or 100 Mbps speed. Enable the loopback at register 0x00.14. Verify that you can receive the data that you transmit. Relevant Part: DP83865 Is it necessary to access any MDIO registers to initialize the DP83865 PHY? Since, the PHY is a self-contained device, it is not necessary to access any MDIO registers to initialize the PHY. The initial settings of the PHY are configured by the strapping option at the pins. The PHY will start normal operation based on the strapping options upon power up or reset Relevant Part: DP83865 What happens to the TX_CLK during 1000 Mbps operation? Similarly what happens to RXD 4:7] during 10/100 Mbps operation? TX_CLK is not used during the 1000 Mbps operation, and the RXD[4:7] lines are not used for the 10/100 operation. These signals are outputs of the Gig PHYTER V. To simplify the MII/GMII interface, these signals are driven actively to a zero volt level. This eliminates the need for pull-down resistors Relevant Part: DP83865 How is the maximum package case temperature calculated for the DP83865? The maximum die temperature is calculated using the following equations: TJ = TA+ Pd(_JA) TJ = TC+ Pd(_c) TC = TJ - Pd(_c) Where: TJ = Junction temperature of the die in ºC TC = Case temperature of the package in ºC Pd = Power dissipated in the die in Watts OJA = 11.7 ºC/watt OC = 2.13 ºC/watt For reliability purposes the maximum junction should be kept below 120 ºC. If the Ambient temperature is 70 ºC and the power dissipation is 4.0 watts then the Maximum Case Temperature will be: TC max = 120 ºC - 1.2 watts (2.13 ºC/watt) TC max = 117.44 ºC Relevant Part: DP83865 Your reference design shows pull-up or pull-down resistors attached to certain pins, which conflict with the pull-up or pull-down information specified in the datasheet? The pull-up or pull-down information specified in the pin description section of the datasheet indicate if there is an internal pull-up or pull-down resistor at the IO buffer used for that specific pin. These resistors are between 25 - 80 k Ω . They will determine the default strap value when the pin is floating. If the default value is to be changed, an external 2 k Ω pull-up or pull-down resistor can be used. Relevant Part: DP83865 I know I have good link, but register 0x01, bit 2 "Link Status" doesn''t contain value ''1'' indicating good link. This bit is defined by IEEE 802.3u Clause 22. It indicates if the link was lost since the last time this register was read. Its name (given by IEEE) is perhaps misleading. A more accurate name would have been the "Link lost" bit. If the actual present link status is desired, then either this register should be read twice, or register 0x11 bit 2 should be read. Register 0x11 shows the actual status of link, speed, and duplex regardless of what was advertised or what has happened in the interim. Relevant Part: DP83865 What is the power up sequence for DP83865? The DP83865 has two types of power supplies, core and I/O. Although, there has not been revealing of power up sequence error such as latch up or dead lock, it is recommended that core power takes precedence over the I/O power when powering up. 1.8V should be up before 2.5V and 3.3V. When powering down, I/O takes precedence over core. 2.5V and 3.3V should be turned off before 1.8V Relevant Part: DP83865 I have forced 10 Mbps or 100 Mbps operation but the associated speed LED doesn''t come on. Speed LEDs are actually an AND function of the speed and link status. Regardless of whether the speed is forced or Auto-Negotiated, there has to be good link for the speed LEDs to turn on. Relevant Part: DP83865 What is a remote bridge? A remote bridge has an Ethernet interface on one side and a serial interface on the other. It would connect to a similar device on the other side of the serial line. It is most commonly used in WAN links where it is impossible or impractical to install network cables. A high-speed modem (or T1 DSU/CSU''s, X.25 PAD''s, etc) and intervening telephone lines or public data network would be used to connect the two remote bridges together. Relevant Part: LAN What does SQE Test / heartbeat mean? What is it? SQE Test (a.k.a. heartbeat) is a means of detecting a transceiver''s inability to detect collisions. Without SQE Test, it is not possible to determine if your collision detector is operating properly. SQE Test is implemented by generating a test signal on the collision pair from the transceiver (or its equivalent) following every transmission on the network. It does not generate any signal on the common medium. The problem with SQE Test is that it is not part of the Ethernet Version 1.0 specification. Therefore, Version 1.0 equipment may not function with transceivers that generates the SQE Test signal. Additionally, IEEE 802.3 specifications state that IEEE 802.3 compliant repeaters must not be attached to transceivers that generate heartbeat. (This has to do with a jam signal that prevents redundant collisions from occurring on the network) . Therefore, you must usually turn-off SQE Test (heartbeat) between the transceiver and an 802.3 repeater. Relevant Part: LAN Are there any restrictions on how Ethernet is cabled? Yes, there are many restriction and they vary according to the media used. First of all, there are distance limitations: - 10Base2 limited to 185 meters (607 ft) per unrepeated cable segment. - 10Base5 limited to 500 meters (1,640 ft) per unrepeated cable segment. - 10BaseF depends on the signaling technology and medium used but can go up to 2KM. - 10BaseT generally accepted to have a maximum run of 100-150M, but is really based on signal loss in Db (11.5db maximum loss source to destination). - 10Broad36 limited to 3,600 meters (almost 2.25 miles). Next, there are limitations on the number of repeaters and cable segments allowed between any two stations on the 10/100 Mbps network. There are two different ways of looking at the same rules: 1. The Ethernet way: A remote repeater pair (with an intermediate point-to-point link) is counted as a single repeater (IEEE calls it two repeaters). You cannot put any stations on the point to point link (by definition!), and there can be two repeaters in the path between any pair of stations. This seems simpler to me than the IEEE terminology, and is equivalent. 2. The IEEE way: There may be no more than five (5) repeated segments, nor more than four (4) repeaters between any two Ethernet stations; and of the five cable segments, only three (3) may be populated. This is referred to as the "5-4-3" rule (5 segments, 4 repeaters, 3 populated segments). It can really get messy when you start cascading through 10BaseT hubs, which are repeaters unto themselves. Just try to remember, that any possible path between two network devices on an unbridged/unrouted network cannot pass through more than 4 repeaters or hubs, nor more than 3 populated cable segments. Finally, 10Base2 is limited to a maximum of 30 network devices per unrepeated network segment with a minimum distance of 0.5m (1.5ft) between T-connectors. 10Base5 is limited to a maximum of 100 network devices per unrepeated segment, with a minimum distance of 2.5m (8.2ft) between taps/Ts (usually indicated by a marker stamped on the cable itself every 2.5m). 10BaseT and 10BaseF are star-wired, so there is no minimum distance requirement between devices, since devices cannot be connected serially. You can install up to the Ethernet maximum of 1024 stations per network with both 10BaseT and 10BaseF. Relevant Part: LAN What does a repeater do? A repeater, used in 10/100 Mbps environments, acts on a purely electrical level to connect to segments. It is used in star topologies and simply amplifies, reshapes, and retimes the analog waveform to extend network segment distances. It does not know anything about addresses or forwarding, thus it cannot be used to reduce traffic like a bridge Relevant Part: LAN What exactly does a bridge do? A bridge connects two distinct segments (usually referring to a physical length of wire) and transmits traffic between them. This allows you to extend the maximum size of the network while still not breaking the maximum wire length, attached device count, or number of repeaters for a network segment Relevant Part: LAN What is UTP and STP? UTP and STP are twisted pair cables. UTP stands for Unshielded Twisted Pair, while STP stands for Shielded Twisted Pair. Typically, UTP is installed by phone companies (though this is often not of high enough quality for high- speed network use) and is what 10BaseT Ethernet runs over. UTP is graded according to its data carrying ability (e.g., Level 3, Level 4, Level 5). 10BaseT Ethernet requires at least Level 3 cable. Many sites now install only Level-5 UTP, even though level 4 is more than sufficient for 10BaseT, because of the greater likelihood that emerging high-speed standards will require cable with better bandwidth capabilities. STP is typically used for Token-Ring networks, where it is commonly referred to IBM Type 1 (or 2, 3, 6, 8, etc); however there are several manufacturers of Ethernet equipment and interfaces that support Ethernet over STP. Nevertheless, Ethernet over STP is not officially defined in any standards. While there is a good level of interoperability with Ethernet over STP, (Lattisnet, developed by Synoptics, is the recognized de facto standard in this area), one should consider the long-term availability and cost of this non-standard scheme before planning new networks around it. Relevant Part: LAN What is a "hub"? A hub is a common wiring point for star-topology networks, and is a common synonym for concentrator (though the latter generally has additional features or capabilities). Arcnet, 10BaseT Ethernet and 10BaseF Ethernet and many proprietary network topologies use hubs to connect multiple cable runs in a star-wired network topology into a single network. Token-Ring MSAUs (Multi-Station Access Units) can also be considered a type of hub. Hubs have multiple ports to attach the different cable runs. Some hubs (such as 10BaseT and active Arcnet) include electronics to regenerate and retime the signal between each hub port. Others (such as 10BaseF or passive Arcnet) simply act as signal splitters, similar to the multi-tap cable-TV splitters you might use on your home antenna coax (of course, 10BaseF uses mirrors to split the signals between cables). Token- Ring MSAUs use relays (mechanical or electronic) to reroute the network signals to each active device in series, while all other hubs redistribute received signals out all ports simultaneously, just as a 10Base2/10Base-T multi-port repeater would Relevant Part: LAN What is a late collision? A late collision occurs when two devices transmit at the same time, but due to cabling errors (most commonly, excessive network segment length or repeaters between devices) neither detects a collision. The reason this happens is because the time to propagate the signal from one end of the network to another is longer than the time to put the entire packet on the network, so the two devices that cause the late collision never see that the other`s sending until after it puts the entire packet on the network. Late collisions are detected by the transmitter after the first "slot time" of 64 byte times. They are only detected during transmissions of packets longer than 64 bytes. Its detection is exactly the same as for a normal collision; it just happens "too late." Typical causes of late collisions are segment cable lengths in excess of the maximum permitted for the cable type, faulty connectors or improper cabling, excessive numbers of repeaters between network devices, and defective Ethernet transceivers or controllers. Another bad thing about late collisions is that they occur for small packets also, but cannot be detected by the transmitter. A network suffering a measurable rate of late collisions (on large packets) is also suffering lost small packets. The higher protocols do not cope well with such losses. Well, they cope, but at much reduced speed. A 1% packet loss is enough to reduce the speed of NFS by 90% with the default retransmission timers. That''s a 10X amplification of the problem. Finally, Ethernet controllers do not retransmit packets lost to late collisions. Relevant Part: LAN Why must the MAC address to be unique? Each NIC (Network Interface Card) has a unique MAC address, so that it will be able to exclusively grab packets off the wire meant for it. If MAC addresses are not unique, there is no way to distinguish between two stations. Devices on the network watch network traffic and look for their own MAC address in each packet to determine whether they should decode it or not. Special circumstances exist for broadcasting to every device Relevant Part: LAN Does mBMC support e-mail alert feature? Email sending is based on SMTP (RFC 821 and RFC 822) protocol. Unfortunately, this requires TCP/IP support from NIC and messages more than 200 bytes. Currently, such messages are not supported by NICs.  The email sending functionality can be easily implemented based on PET SNMPv1 alerts supported by mBMC. A remote console (iConsole for example) receives SNMP alerts from the mBMC and forwards them to email addresses. A benefit of such implementation is that remote console can forward alerts not just to email addresses, but to another alert devices such as number pages, SMS messages of mobile phones and etc. And more convenient for end user for configuration. Relevant Part: PC87431 What is Power Consumption? Power consumption is the power required to operate the device under a specified load. For devices with one positive supply pin (V+), the steady-state power consumption is the product of V+ and the device supply current, typically with no load. Adding a load will often increase the device supply current, thus increasing the device power consumption. Power consumption is important to the system designer for two reasons: (1) The system power supply must provide enough power to allow all devices to operate correctly; and (2) A device''s power consumption causes the device to heat up, according to its thermal resistance (and this may lead to overheating of the device). Power consumption may be reduced by operating at lower supply voltages - consult the device datasheet for details Where can I get information on LLP packaging? Information relating to LLP packaging can be found at the following link to the corporate web site: http://www.national.com/packaging/llp/ Where can I find online selection guides for National products? National Semiconductor''s web site offers many selection guides. Parametric Product Selection Table is an interactive selection tool for all National products Selection Guide brochures are listed in the Reference Documents column of the Document Library Amplifiers Selguide or Palm Guide selection tools can be downloaded for offline use When package choice is important, see the Selection Guide by Package Type WEBENCH Online Design Tools incorporate product selection as part of the design process