Data Conversion What tools does National offer to aid in the design of active filters? In the WEBENCH suite of online design tools is the Active Filter Designer. The Active Filter Designer supports design and simulation of semi-custom lowpass and highpass filters from 2nd to 10th order in a large variety of filter response types, including Chebyshev, Butterworth, Bessel, and others. Begin your filter design here. What is SPI or Serial to Parallel Interface? The Serial Peripheral Interface Bus (SPI) is a synchronous serial data link standard that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. The Microwire and MicrowirePLUS buses are a subsets of SPI. National offers many solutions with SPI interface including: Low power ADCs Low power DACs Digital Temperature Sensors Audio codec subsystems PLLatinum PLLs and Jitter Cleaners High-Speed Interface and SDI ICs Mobile Pixel Link (MPL) for small-format LCD displays DVGAs Where can I find a utility for converting IBIS models to SPICE? Intusoft offers a free IBIS to SPICE conversion utility. See their Modeling Utilities page, http://www.intusoft.com/utilities.htm. What is the difference between a transformer and a balun? The basic difference between a transformer and a wire-wound balun is the way the coils of each are wound and the way they are used. A transformer has primary and secondary windings that are isolated from each other. The secondary can be D.C biased differently than the primary, usually through a secondary center tap. The secondary winding may also have taps for providing different voltages to different parts or a circuit, or completely isolated secondaries to drive different parts of the circuit. The transmission line balun has a D.C connection between the primary and one secondary port and does not not, typically, provide multiple secondary ports or signal taps. The balun is capable of very broad band performance, compared with the ordinary transformer, with very little signal loss. Transformers are specified with, among other things, a given turns or voltage ratio, where baluns are specified in terms of impedance ratios. A balun with a 1:2 impedance ratio will have an impedance on its differential port that is twice the impedance at the single-ended port. Relevant Part: ADC08500,;ADC08D500,;ADC081000,;ADC08D1000,;ADC08D1020,;ADC081500,;ADC08D1500,;ADC08D1520,;ADC083000,;ADC08B3000 How can I get the FPGA code for one of your Gigasample ADC development boards? Contact your sales engineer for National Semiconductor products, who will work with you to establish an NDA and provide you with the code Relevant Part: ADC08D500,DEV,;ADC08D1000DEV,;ADC08D1500DEV,;ADC081020DEV,;ADC08D1520DEV,;ADC083000RB,;ADC08B3000RB Why is input impedance not specified on the ADC1203x or ADC1213x? The input is connected through the multiplexer to a switched capacitor ladder. For a steady DC input value, the input impedance is in the megohms. But a varying input must charge [or discharge] the input capacitive ladder and the value of the capacitance varies with the input voltage and the reference voltage. When the resistance of the input multiplexer is combined with the capacitance of the ladder, the resulting input is not a fixed value but an R-C that must be charged [or discharged]. A low source impedance such as an op amp can drive the R-C to its final value very quickly. But a high source impedance, typical of many transducers, will require more time. That is why the acquisition time is programmable. The source impedance issue is discussed in the data sheet Section 6. Relevant Part: ADC12030;ADC12032;ADC12034;ADC12038;ADC12130;ADC12132;ADC12138 Do you have any data on the ADC12281 SFDR performance at higher frequencies than 10 MHz specified in the datasheet?(if it is possible at 70 MHz). The ADC12281 is a poor choice when using input frequencies above 12 to 15MHz, as the input circuit just will not handle it well. What you will end up with at higher input frequencies is a lot of noise and a bit of distortion. We would recommend the ADC12L063 or the ADC12L066 for input frequencies in the 70MHz area. The ADC12L063 is a 12-bit, 62Msps ADCwith a 170MHZ Full Power Bandwidth. The ADC12L066 is a 66 Msps ADC with a 450 MHz Full Power Bandwidth and specifications with an input frequency of 150 MHz Relevant Part: ADC12281;ADC12L063;ADC12L066 The applications provided on the datasheets of many of the Analog to Digital converters show three capacitors on the Va, Vd and Vref pins. Are all of these capacitors required? One or two capacitor might be sufficient, depending upon the particular device and the board layout. The larger capacitor, typically 5 to 10µF, provides low impedance bulk energy storage for voltage stability during conversions and transitions. The smaller capacitors absorb any higher frequency noise spikes. If the pc board is very well laid out for low noise operation, and does not contain a microcontroller or other noisy digital logic, fewer capacitors may be required. But to obtain the guaranteed accuracy level for the ADC being used, it is generally best to follow data sheet recommendations. Relevant Part: ADC How can I eliminate the overshoot and/or undershoot on the clock line and the control lines to my Analog to Digital Converter? The overshoot and/or undershoot is caused by fast signal edges combined with a poorly matched signal termination. Add a 47 to 100 Ω resistor in series with the input, located as close to the clock source as you possibly can. The purpose is to match the source impedance to that of the clock line, which should be considered a transmission line. The series termination uses little additional power and is usually sufficient to minimize the ringing effect. Relevant Part: ADC What could cause the performance from the ADC evaluation board to be less than the typical data sheet specifications? Although "typical" performance does not guarantee a minimum performance level, National''s evaluation boards generally perform equal to or better than the typical performance of the data sheet. When this is not the case, there can be a number of reasons for this. The primary cause of lowered ADC evaluation board performance is the failure to use an adequate (bandpass) filter between the analog input signal source and the board. Many people assume that their $10,000+ signal source is a very "clean" one, but this is not usually the case. Another cause would be the use of some active circuitry between the signal source and the ADC input, whether that circuitry is on the board or is a separate module. The more that is in a signal path, the more that signal will be degraded Relevant Part: All;ADCs Is there a replacement for the LM12438 DAS (Data Acquisition System)? There is no direct replacement for this serial output DAS, but a parallel output version is available in the LM12458. Relevant Part: LM12438;LM12458 Where can I get a schematic of a National ADC evaluation board? Go to the ADC Featured Community and click on "Evaluation Board Table" under Design Resources. In that table you will find a "Manual" column and individual evaluation board rows. Click on the appropriate cell to download the manual for the board you want. The evaluation board schematic is located in that manual. Many ADCs have a large input spike. When I try to get rid of it with a large capacitor, the conversion result is not what I expect. Why is this? The sampling input of most of today''s ADCs have a switch through which an input capacitor is charged while the ADC is in the sample mode. In the hold mode, the input switch is opened and the charge on this input capacitor is transferred to an internal hold capacitor. When the input switch is again closed, the charge on that input capacitor is different from what it was before the switch opened, so an input current pulse is needed to re-charge that capacitor. This results in a voltage pulse seen at the ADC input. Do not attempt to completely filter out this pulse as the current averaging that results could provide an inaccurate sampled voltage and erroneous conversions What are Dynamic Specifications of an A/D Converter? Dynamic Specifications of an ADC are those pertaining to an AC input signal. These include S/N ratio (SNR), SINAD (signal to noise+distortion), ENOB (effective number of bits), THD (total harmonic distortion), IMD (intermodulation distortion), FPBW (full power bandwidth), and SSBW (small signal bandwidth) What are Missing Codes? Missing Codes are those output codes that are skipped or will never appear at the ADC outputs. These codes cannot be reached by any input value What are Static Specifications of an A/D Converter? Static Specifications are the specifications of an ADC pertaining to a DC signal input. These include gain error, offset error, and differential and integral linearity errors What is Aperture Delay? Aperture Delay: See Sampling (Aperture) Delay What is Aperture Jitter? Aperture Jitter is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise What is Bottom Offset? Bottom Offset is the difference between the input voltage that just causes the output code to transition to the first code and the negative reference voltage. Bottom Offset is defined as EOB=VZT-VRB , where VZT is the first code transition input voltage and VRB is the lower reference voltage. Note that this is different from the normal Offset Error What is Clock Duty Cycle? Clock Duty Cycle is the ratio of the time that the clock waveform is high to the total time for one clock cycle What is Common Mode Voltage (VCM)? Common Mode Voltage (VCM ) is the d.c. input voltage that is common to both pins of a differential input What is Conversion Latency? Conversion Latency: See Pipeline Delay What is Conversion Time? Conversion Time is the time required for a complete measurement by an analog-to-digital converter. Since the Conversion Time does not include acquisition time, multiplexer set up time, or other elements of a complete conversion cycle, the conversion time may be less than the Throughput Time What is DC Common-Mode Error? DC Common-Mode Error is a specification which applies to ADCs with differential inputs. It is the change in the output code that occurs when the analog voltages on the two inputs are changed by an equal amount. It is usually expressed in LSBs What is Differential Gain Error? Differential Gain Error is the percentage difference between the output amplitudes of a specified small signal, high frequency sine wave input at two different dc input levels What is Differential Non-Linearity (DNL)? In Analog-to-Digital Converters (ADC), Differential Non-Linearity (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DNL is commonly measured at the rated clock frequency with a ramp input. In Digital-to-Analog Converters (DAC), DNL is a measure of the worst case deviation from the ideal 1LSB step.  Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart.  A differential nonlinearity greater than 1 LSB will lead to a non-monotonic transfer function in a DAC. What is Differential Phase Error? Differential Phase Error is the difference in the output phase of a reconstructed small signal sine wave at two different dc input levels What is Effective Number of Bits (ENOB, or Effective Bits)? Effective Number of Bits (ENOB, or Effective Bits) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD -1.76)/ 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits What is Full Power Bandwidth (FPBW)? Full Power Bandwidth (FPBW) is the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input What is Full Scale (FS) Input Range? Full Scale (FS) Input Range of the ADC is the input range of voltages over which the ADC will digitize that input without going underrange or overrange. For V REF + = 3.5V and VREF - = 1.5V, FS = (VREF + )-(VREF - ) = 2.0V What is Full Scale Error? Full Scale Error is a measure of how far the last code transition is from the ideal 1 1/2 LSB below VREF + and is defined as: VFSE =Vmax + 1.5 LSB - VREF + where Vmax is the voltage at which the transition to the max code occurs and can be expressed in Volts, LSB or percent of ful scale range What is Full Scale Step Response? Full Scale Step Response is defined as the time required after VIN goes from VREF- to VREF+ ,or VREF= to VREF-, and settles sufficiently for the converter to recover and make a conversion with its rated accuracy What is Gain Error? Gain Error is the difference between the ideal and actual differences between the input levels at which the first and last code transitions occur. That is, how far this difference is from full scale - 2 LSB What is Gain Temperature Coefficient (Full Scale Temperature Coefficient)? Gain Temperature Coefficient (Full Scale Temperature Coefficient) is the change in gain error divided by change in temperature. Usually expressed in parts per million per degree Celsius (ppm/°C) What is Integral Non-Linearity (INL)? Integral Non-Linearity (INL) is a measure of the maximum deviation of each individual code from a line drawn from zero scale or negative full scale ( 1/2 LSB below the first code transition) through positive full scale (1 1/2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. The end point test method is used. INL is commonly measured at rated clock frequency with a ramp input What is Intermodulation Distortion (IMD)? Intermodulation Distortion (IMD) is the creation of additional spectral components that are not present at the input as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in one of the original frequencies. IMD is usually expressed in dB What is LSB (Least Significant Bit)? LSB (Least Significant Bit) is the bit that has the smallest value or weight of all bits. This value is m*VREF/2 n where ''m'' is the reference scale factor (which is most often unity) and ''n'' is the ADC resolution What is MSB (Most Significant Bit)? MSB (Most Significant Bit) is the bit that has the largest value or weight. Its value is one half of full scale What is Offset Error? Offset Error of an offset binary ADC is a measure of how far the mid-scale transition point is from the ideal zero voltage input What is Output Delay? Output Delay is the time delay after the edge of the input clock before the data update is present at the output pins What is Output Hold Time? Output Hold Time is the length of time that the output data is valid after the edge of the input clock What is Overrange Recovery Time? Overrange Recovery Time is the time required after VIN goes from a specified voltage out of the normal input range to a specified voltage within the normal input range and the converter makes a conversion with its rated accuracy What is Pipeline Delay (Latency)? Pipeline Delay (Latency) is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available the Pipeline Delay plus the Output Delay after that sample is taken. New data is available at every clock cycle, but the data lags the acquisition by the Pipeline Delay plus the Output Delay What is Power Supply Rejection Ratio (PSRR)? Power Supply Rejection Ratio (PSRR) can be one of two specifications. DC PSRR is the ratio of the change in a specified parameter (e.g., Full Scale Error) that results from a specified change in the power supply voltage. AC PSRR is measured with a signal of specified frequency and amplitude riding upon the power supply and is the ratio of the output amplitude of that signal at the output to its amplitude on the power supply pin. PSRR is usually specified in dB What is Quantization Error? Quantization Error is the error inherent in all A/D conversions. Since even an ''ideal'' converter has finite resolution, any analog voltage that falls beween two adjacent output codes will result in an output code that is inaccurate by up to 1/2 LSB. This is the quantization Error What is Ratiometric Operation? Ratiometric Operation uses the reference voltage that is used for the ADC to drive the signal source such that the ratio of the output of that signal source to the reference is independant of the reference voltage. When the driving voltage for that source is also used as the voltage reference for the ADC, the ADC output code is a function of the ratio of the signal source output to the reference voltage and, for a limited reference voltage range, the ADC output code is independent of the value of that reference voltage What is Resolution? Resolution is the analog increment corresponding to a 1 LSB converter code change. Resolution has also been defined as the number of bits (n) of the converter. The number of digital codes is equal to 2^n , where "n" is the number of bits. As an example, a 12-bit converter maps the analog signal into 2 ^12 = 4096 digital codes. Resolution of a 12-bit ADC, then, is the full range of input values that do not cause the output code to saturate divided by 2^12, or 4096 What is Sampling (Aperture) Delay? Sampling (Aperture) Delay is the time required after the edge of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the ''hold'' mode the sampling delay after the specified clock What is Signal To Noise Plus Distortion (S/(N+D) Or SINAD)? Signal to Noise Plus Distortion (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding dc What is Signal To Noise Ratio (SNR)? Signal to Noise Ration (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or dc What is Small Signal Bandwidth (SSBW)? Small Signal Bandwidth (SSBW) is the frequency at which a specified amplitude input signal drops a specified amout below the output level of a specified, low frequency signal of the same input amplitude What is Spurious Free Dynamic Range (SFDR)? Spurious Free Dynamic Range (SFDR) is the difference, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input What is Throughput Rate? Throughput Rate is the maximum continuous conversion rate of the ADC What is Throughput Time? Throughput Time is the time it takes a converter to do a single conversion. Throughput time includes any multiplexer settling time, acquisition time, conversion time, and output presentation time What is Top Offset? Top Offset is the difference between the positive reference voltage and the input voltage that just causes the output code to transition to full scale and is defined as EOT = VFT - VREF+ where VFT is the full scale transition input voltage and VREF+ is the positive reference voltage. Note that this is different from Full Scale Error or Full Scale Gain Error What is Total Harmonic Distortion (THD)? Total Harmonic Distortion (THD) is the ratio, expressed in dB or dBc, of the total of the first few harmonic levels (nine harmonics for National Semiconductor ADCs) to the level of the input signal at the output. THD is calculated as: THD=sqrt[ ( f2xf2 + f3xf3 + f4xf4 + f5xf5 + f6xf6 + f7xf7 + f8xf8 + f9xf9 + f10xf10) / (f1xf1) ] where f1 is the fundamental (input) frequency and f2 through f10 are the first 9 harmonic frequencies What is Total Unadjusted Error (TUE)? Total Unadjusted Error(TUE) is the maximum deviation of the voltage corresponding to the center of a digital code’s associated input voltage span from the ideal case. Total unadjusted error includes offset error, Gain error, and differential and integral nonlinearity errors What is Zero Error? The Zero Error of a bipolar output ADC is the difference between the theoretical input voltage (typically mid-scale plus 1/2 LSB) and the actual input voltage that causes a transition from an output code of zero to an output code of one What is Zero Scale Offset Error? Zero Scale Offset Error of a unipolar output ADC is the difference between the ideal input voltage (1/2 LSB) and the actual input voltage that just causes a transition from an output code of zero to an output code of one Does use of a single ground plane on a pc board have any advantages for low frequency designs (below 1 MHz)? Yes, the single ground plane helps to minimize EMI problems, but it is easier to do the layout for low frequencies with a split ground plane. However, use of the single ground plane with careful attention to current flows will allow you to get excellent performance results with a single ground plane while minimizing EMI How should multiple ground planes of a pc board be connected? It is not recommended to use multiple ground planes. It is best to use of a single, unified ground plane. Please refer to the archived online seminar entitled "Controlling Noise and Radiation in Mixed Signal and Digital Systems". Should the power supply ground plane of a pc board be the same plane as the digital and analog ground plane? Yes, they should be the same. It important, however, to carefully route all power and signal traces to keep ground currents separate from each other What is the impact of not having a power plane on a pc board? Not having a power plane reduces the coupling capacitance between power and ground. This is the disadvantage of this approach. You can still use large areas (extremely wide traces) for the power run, but it is important to keep analog and digital currents in their respective areas of the board if noise is to be minimized, which is why we recommend power traces rather than a power plane When designing a multi-layer pc board, what is a good stacking order for power and ground planes relative to analog circuitry? With a four layer board, it is good to have signal traces on the top and bottom layers, Ground plane in the second (or third) layer, and power traces (and sometimes other traces) in the third (or second) layer. For six layer boards, the planes 1 through 6 would be in this order, signal, ground, power (or signal), signal (or power), ground, signal When designing a pc board, is it OK to split the ground and power planes? Splitting both ground and power planes can work if you are careful to detail. Routing a signal line over the wrong ground can cause problems with both noise and EMI. One of the problems here is that any given line may have a combination of digital and analog currents associated with it Why doesn''t the LM2907 respond to a 0-5 volt AC input signal? The 8 pin LM2907 has a comparator to sense the input signal . The reference input of the comparator is tied to ground so the signal being measured must oscillate above and below ground to be detected.The 14 pin LM2907 can be used to sense a signal that does not oscillate below ground. This part has the reference input brought out on pin 11 so the user can control the reference voltage Why does the LM4040 reverse voltage drift after temperature cycling? This is due to the annealing process used to purify the silicon. As a result, customers will notice a shift due to temperature cycling. The shift should still be within the initial tolerance specified for the reference, as long as the test conditions are similar to those given in the data shee Relevant Part: LM4040 How do I determine the value for a shunt reference''s series resistor? For a shunt reference to provide a stable voltage, a certain amount of current MUST be flowing THROUGH the reference. This current is determined by a resistor between the power source and the reference input. For example, for the LM385, there should be 50uA to 1mA of current flowing through the LM385. 100uA is the current at which all the specifications are made, and is a good operating current for the reference. To figure the value of the resistor Rs, you must also make allowances for any current shunted away from the reference by the circuit connected to the reference output. The equation is:    Rs = (Vsupply - Vreference) / (Iload + Ireference). For a 1.2V reference with a 5V supply, and no significant load, Rs = (5V - 1.24V) / 100uA = 37.6kohm. The actual value of the resistor is not very critical. 10k to 39k would work fine. To determine load current, be sure to check the "Reference Current" (Iref) spec, or calculate it from the "reference input resistance" spec, of your A/D or D/A converters! Rs values of a few kilohms are not uncommon for use on converter inputs, and should be buffered with an op-amp if possible to provide a low impedance source. Relevant Part: REFERENCE;LM385 What does "ppm" stand for? How can I convert the units to the ones that we are familiar with? PPM is "parts per million", or 1/1,000,000, or 0.000001. It''s also equivalent to 0.0001 percent. 1ppm is equivalent to 1uV out of 1V Relevant Part: REFERENCE