GHz Sampling Design Challenges

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Today, as data conversion sampling rates of analog-to-digital converters are moving into the Giga Sample Per Second (GSPS) range, data conversion systems must be so designed as to be able to support such kind of high conversion rates. Furthermore, only those analog components that can generate and amplify high-frequency signals should be used. In addition to the role played by the analog signal path, other areas that the designer must consider very carefully are the sampling clock and the capture of digital data at high bit rates. This Webinar will discuss the challenges facing the engineers when they design GHz sampling systems. Tips, tricks and techniques for powerful designs will also be offered.

Topics covered in this online seminar include:

• Introduction of National Semiconductor's Ghz Ultra High Speed ADCs
• ADC08Dxxx Circuit Design Considerations
• The Clock Circuitry
• Effects of Time Interleaving
• The Amplifier Front-End
• The Digital Data Capture (FPGA implementation)