Metrics: Reliability

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Available Reports

PPM/FITS Summary: A graphical trend of National Semiconductor's Reliability Performance.

PPM/FITS - By Process: Failure Rates of Major Processes at National Semiconductor.

Package Data: Failure Rates of all Packages at National Semiconductor.

In reviewing this data, it may be helpful to refer to our Process by NSID Cross Reference Table (pdf: 1.8MB) and information on our Reliability Testing Programs.

Purpose of this Metric

  • To provide a periodic monitor of product reliability under accelerated test conditions on wafer fabrication and assembly processes.
  • To provide fab process and package reliability performance characteristics to customer.

Audit Strategy

  • Package/Assembly processes are audited by Autoclave (ACLV), Temperature and Humidity Bias Test (THBT) and Temperature Cycling (TMCL) tests.
  • Wafer fabrication processes are monitored by EFR and Long Term High Temperature Operating Life (OPL) tests.
  • Devices are selected within each package and process audit groups based on representability and high manufacturing volume. Each audit group contains at least 3 devices.

Test Frequency

TEST FREQUENCY
EFR
(All major processes)
Every week
OPL (500hr @ 150C or equivalent based on Arrhenius model)

THBT (1000 hr)

ACLV (96 hr)

TMCL (500 cycles @ -65C to 150C or equivalent based on Coffin-Manson model)
Every 8 weeks

Every 8 weeks

Every 8 weeks

Every 8 weeks

PPM/FITS Summary 

National Semiconductor conducts a Long Term Audit (LTA) program in order to identify trends in reliability of our products. The chart below displays the Early Failure Rate (PPM) and Long Term Life Failure Rate (FITS) trends for these products.

The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

The trend lines for both PPM and FIT rates illustrate the positive year to year reliability improvements at National Semiconductor.

PPM/FITS by Process 

The following table lists Early Failure Rates in parts per million (PPM ) and Long Term Failure Rates in units per billion device hours (FITS) for the wafer fabrication processes.

The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

The data used to calculate the failure rates was obtained from OPL tests performed in the Reliability Monitoring Program; and from Reliability Qualification where applicable

These failure rates are updated quarterly with data through the end of the preceding quarter.

Period Covered: 29th Feb 2004 to 29th May 2011
Last Updated: 1st Oct 2011
Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
.350202750015150003429885386
.50145950010450004296521603
ABCD15004268000639400011814314958
ABCD150XV1038680025950002736338335
ABCD150XV2036010011554964327875145
ABCD5053640016269843461661152
ABIC0168980030080002853528213
BICMOS8215238132018125002514301823
BICMOS8B+036320027622922783807897
BIFET0128750010650004302196657
CBIC092250015150003429885386
CMOS0203000027850002790251354
CMOS70213010015840003449464325
CMOS811372573017745002503519220
CMOS8T0167100017800002505079860
CMOS917912127011930003338517007
CMOS9T021600023971522680198425
CS065247473430552700011568301341
CS0800307150029005002823024794
CS1001142117108980004254809951
CS15011629062011575004328443785
CS200*098500033750002957665465
DLM0105650019900002546224006
HV7000142550015825003449038695
LB2500203650019250002546224006
LB30003437100416450011181688246
LFAST10201400027850002790251354
LMDMOS0182950026500002751944735
LS JI SLM*0800001000003628375273
P2CMOS0508600145035002578995367
PVIP0500142800017550003497986041
RFCMOS020550037000010104988510
SLM04404600353250011002356520
TS060D010615007700005218489602
TS10008370009000004255377457
VIP 100134110012450003353272149
VIP III0161600013025003369587931
VIP III H/HU202366007025546199351615
VIP1+03301000382000011083935430
VIP50CLZ305670009450004268146330

Note: PPM is a point estimate based on rejects and sample size for EFR.
* - Data from previous time range 02/24/2003 - 02/27/2004

Package Data - Reliability Monitor Plan 

The following tables list failure rate in percentage (PCT) for packages. The data used to calculate the failure percentage was obtained from ACLV, THBT and TMCL tests.

These tables are updated quarterly with data through the end of the preceding quarter.

Percentage = Rejects/Sample size * 100
Period Covered: 29th Feb 2004 to Feb 2011
Last Updated: 3 October 2011

Autoclave
Package Rejects Sample Size PCT
BGA 1 5130 0.02
CSP 0 4869 0
CSP* 0 2880 0
LLP 0 3405 0
LLP* 0 2523 0
MDIP 1 3145 0.03
MICROSMD 0 1650 0
PLCC 0 2080 0
QFP 0 11936 0
SC70 0 3315 0
SOIC 1 19022 0.01
SOT23/TSOT 0 8317 0
SOT223 0 3530 0
SSOP/TSSOP 1 14182 0.01
TO220 0 5765 0
TO247 0 1125 0
TO252 0 3405 0
TO263 0 3540 0
* Stressed for 24hrs

 

Temperature Humidity Bias Test
Package Rejects Sample Size PCT
BGA 1 990 0.10
CSP 0 1720 0
LLP 1 3060 0.03
MDIP 0 4450 0
MICROSMD 0 805 0
PLCC 0 2440 0
QFP 0 6330 0
SC70 0 3225 0
SOIC 1 17289 0.01
SOT23/TSOT 0 8766 0
SOT223 0 3593 0
SSOP/TSSOP 0 12775 0
TO220 0 5910 0
TO247 0 1350 0
TO252 0 3305 0
TO263 0 4259 0

 

Temperature Cycle
Package Rejects Sample Size PCT
BGA 0 5297 0
CSP 0 5222 0
LLP 2 4890 0.04
MDIP 1 3415 0.03
MICROSMD 3 1630 0.18
PLCC 0 2350 0
QFP 0 12403 0
SC70 0 3405 0
SOIC 0 18588 0
SOT23/TSOT 0 8640 0
SOT223 0 3585 0
SSOP/TSSOP 0 12093 0
TO220 3 5585 0.05
TO247 0 1260 0
TO252 0 3495 0
TO263 0 3990 0

 



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