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Voltage regulators with an external reference feature are advantageous in double data rate DDR, DDR2, and DDR3 SDRAM memory bus supply and termination specifications. For double data rate applications, data is accessed using both the rising and falling edge. These memories use a single power source for their supply voltages (VDD, VTT, & VREF) to ensure that all voltage levels track each other. The length of the memory interconnects, coupled with the multiple stubs that are required for supporting DIMMs result in a signal reflection causing data corruption. The solution to this is typically an active termination scheme called SSTL (Stub Series Termination Logic) used in DDR memory buses.
DDR Memory Supply Specifications & Recommended Products
| DDR SDRAM Standard |
DDR Interface |
VDDQ Supply |
VTT & VREF Active Termination Supplies |
| DDR3 |
SSTL_15 |
1.5V |
VDDQ/2 |
| DDR2 |
SSTL_18 |
1.8V |
VDDQ/2 |
| DDR1 |
SSTL_2 |
2.5V |
VDDQ/2 |
| SDRAM |
LVTTL |
3.3V |
3.3V |
DDR VDDQ Power Supply Products
DDR VTT & VREF Active Termination Products
DDR Design Resources
- Article: National's LP2995 Linear Regulator: A simple solution to DDR-SDRAM Termination
- AN-1254: DDR-SDRAM Termination Simplified Using a Linear Regulator (App note on DDR termination in general, uses LP2995 as example)
- AN-1813: LP2998 Evaluation Board (shows design for DDR1 and DDR2 VTT)
- AN-1357: LM2744 Evaluation Board (page 2 shows schematics for DDR SDRAM VTT supply)
- AN-1603: LM274x Family Reference Designs (page 16 shows DDR2 VTT circuit)
- AB-113: DDR-SDRAM Termination Simplified Using a Linear Regulator
- Power Designer 122: Optimizing Power Controller Designs through Effective Utilization of Performance Features (page 6 shows LM2744 used for DDR2 VTT)
- AN-1241: LP2995 Evaluation Board
- AN-1268: LP2996 Evaluation Board
Related Resources
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