- IBIS Interface Models -IBIS (Input/Output Buffer Information Specification) is a behavioral model in ASCII file format that describes the input/output characteristics of a device
- XTK Interface Models - Mentor Graphics behavioral models for XTK simulation tool
- DML Interface Models - Cadence behavioral models for SpecctraQuest simulation tool
- BSDL Interface Models - IEEE 1149.1 Standard for Boundary Scan Test
- SPICE - not currently available for interface products - some SPICE platforms accept IBIS files as input files
- Download models by part number or type from table below
Related Modeling Links
Non-inclusive list of links to industry related web sites on high-speed topics:
Simulators
Services/Consultants
- NESA: System design, Signal Integrity & more
- Signal Consulting Inc: Dr. Howard Johnson, author of High-Speed Digital Design: A Handbook of Black Magic
- Teraspeed: High-speed design, measurement based IBIS files and interconnect, and training
- Sisoft: High-speed design consulting, IBIS development services, and training
- Be The Signal: Eric Bogatin signal integrity classes and blog
Other Interface Software
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IBIS Information
The IBIS specification was developed so that semiconductor manufacturers could provide models of their devices with fast simulation times, multi platform support, and without sharing intellectual property (circuit design and process), such as the case with SPICE models. Since an IBIS file is a behavioral model, it also has the benefit of simulating at much faster times than a SPICE model file.
The IBIS specification is a recognized standard, ANSI/EIA-656A. The IBIS Open Forum (an EIA group) is responsible for the official IBIS specification. The IBIS Open Forum meets every three weeks to discuss current issues and future enhancements of the IBIS specification and related modeling issues.
White Papers
Application Notes
Short Topics
Sample Simulations
Support
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