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SerDes Quick Selection Table
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| Segment |
Family & Description |
| Industrial |
Channel Link III: High speed payload along with embedded clock and control channel
Channel Link II: High speed payload along with embedded clock
Channel Link I: 21/28/48 bit SerDes with parallel clock (nD+C scheme)
FPGA-Link: Optimized for FPGA based applications, 8b/10b based SerDes with extended reach and SigCon features |
| Communications |
SCAN25100: CPRI based 8b/10b SerDes for optical or copper applications
10 / 16 / 18 bit SerDes: General Purpose 10/16/18 bit SerDes with embedded clock |
Automotive
AECQ Grade |
FPD-Link III: SerDes for Display and Imaging Applications with Control Channel
FPD-Link II: SerDes for Display and Imaging Applications |
| Displays |
FPD-Link: 21 and 28 bit SerDes with parallel clock (3D+C, 4D+C)
Open LDI: 48 bit version of FPD-Link (8D+C) supporting dual pixel applications |
| Professional Video |
SMPTE / SerDes: Stand alone SerDes for SMPTE / SDI Applications
SMPTE / SerDes: FPGA-Attach SerDes for SMPTE / SDI Applications |
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Through three generations of Channel Link Serializers and Deserializers (SerDes), National Semiconductor has enabled robust high-speed data serialization in a wide variety of industrial data, video and imaging applications. The latest Channel Link II and Channel Link III SerDes deliver twice the cable length performance at half the system cost and are among the lowest-power SerDes chipsets in the industry.
Channel Link Family Integration
Channel Link
Parallel Clock |
Channel Link II
Embedded Clock |
Channel Link III
Embedded Clock & Control |
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- Reducing a wide parallel bus
- Small connector
- Extended reach
- No reference clock or training patterns
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- Embedded Clock and wide bus over single pair
- Inexpensive cable and connector support
- Integrated SigCon features
- EMI mitigation features
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- Embedded Clock
- Bidirectional zero-latency control bus over a single pair
- Integrated SigCon features
- EMI mitigation features
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| Applications: Remote Cameras & Displays, Factory Automation, Medical Imaging, Video Systems |
Channel Link II & III Selection Table
| Serializer |
Deserializer |
Embedded
Control |
Parallel I/O |
Parallel
Bus (bits) |
CLK Range
(MHz) |
Max BW
(Gbps) |
Mux Ratio |
Features |
|
|
– |
LVCMOS |
24 |
10 - 75 |
1.8+ |
24:1 |
Supports HS, VS and DE also. |
|
|
– |
LVCMOS |
24 |
5 - 50 |
1.2+ |
24:1 |
Supports HS, VS and DE also. |
|
|
– |
LVDS |
4 |
10 - 75 |
1.8+ |
4:1 |
LVDS Input & Output |
|
|
– |
LVDS |
4 |
5 - 50 |
1.2+ |
4:1 |
LVDS Input & Output |
|
|
– |
LVCMOS |
32 |
20 - 85 |
2.72 |
32:4 |
Wide 32-bit data bus |
|
|
– |
LVCMOS |
32 |
20 - 50 |
1.6 |
32:2 |
Wide 32-bit data bus |
|
|
Yes |
LVCMOS |
21+ |
10 - 50 |
1.0+ |
21:1 |
Embedded Zero Latency Bidirectional Control Channel |
|
|
Yes |
LVCMOS |
16+ |
10 - 50 |
0.8+ |
16:1 |
Embedded Zero Latency Bidirectional Control Channel |
| National's highly analog optimized FPGA-Link SerDes devices complement the digital flexibility offered by FPGAs to enable an optimally partitioned system. The FPGA-Link SerDes supports data rates up to 3.125 Gbps and incorporates highly effective signal conditioning (transmit de-emphasis, receive equalization) and clock conditioning (jitter cleaning) to drive popular interconnect, like CAT-5/6/7, Coax (50-ohm, 75-ohm), Fiber, and FR-4, over long distances. This family also supports advanced system configurations like failover (redundant I/Os) and daisy chaining (retimed output). These features make these devices ideal for communication systems, industrial cameras, LED walls (stadium displays), medical imaging, video transport, and display applications. |
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FPGA-Link Selection Table
| Part Number |
Function |
Input |
Output |
Bandwidth |
Features |
|
Serializer |
5D+C, DDR, LVDS |
1 CML |
3.125 Gbps |
De-E Driver |
|
Deserializer |
1 CML |
5D+C, DDR, LVDS |
3.125 Gbps |
Equalizer Input |
|
Serializer |
5D+C, DDR, LVDS |
1 + 1 CML |
3.125 Gbps |
De-E Driver, Redundant output |
|
Deserializer |
1 + 1 CML |
5D+C, DDR, LVD |
3.125 Gbps |
Equalizer Input, Redundant Input, Loop Through Output |
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Select
Serializer / Deserializer (SerDes) (All)
Application Specific SerDes
Complementary Devices
PDF Selection Guides
- Including analog products selection guide, industrial solutions, broadcast video/SDI, automotive solutions, and more. PDF guides
Related Sites
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Design
SerDes App Notes & Technical Documents
- SPD-123: To Shield or Not to Shield: Industrial Video SerDes and EMI
- SPD-122 : Go the Distance: Industrial SerDes with Embedded Clock and Control
- AN-1887: Expanding the Payload with National's FPGA-Link SerDes
- AN-2007: Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des
- See all interface application notes
SerDes Design Guides
 LVDS Owner's Manual (4th Ed)
Explains LVDS, CML, signal conditioning, and much more…
FPGA-Link SerDes Tools
The DS32ELX0421/0124 Ser/Des integrates advanced signal conditioning with an FPGA friendly interface for serial links up to 3.125 Gbps. The EXP High-Performance SerDes Module allows for rapid evaluation and system development for this chipset when paired with Xilinx Spartan-3A devices.
Transmission Line RAPIDESIGNER Slide Rule
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Explore
Enhancing the Video Interface in Harsh Industrial Environments (Available on-demand)
 Presented by National and ECN Magazine. Find out how to implement ruggedized video interfaces using the new Channel Link II and III Serializer/Deserializer (SerDes) families.
SerDes Videos
More SerDes Resources
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