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The System Test Access (STA) Evaluation Kit provides a scaled-down representation of a typical multi-drop system for the purpose of showing multi-drop and embedded JTAG testing, diagnostics and FPGA configuration. The kit is composed of a backplane with 3 slots and several daughtercards to simulate various implementations of test architectures. The modular design allows simple demonstrations, yet is expandable for use as a development kit where complex implementations of test architectures and new products can be evaluated.
The STA Evaluation Kit is intended to be generic and compatible with Industry standards and 3rd party software and hardware. Pre-generated SVF files are provided for three example configurations, however, Netlists and schematics are also included if the user would prefer to generate their own test vector files for their own hardware.
The STA Evaluation Kit supports the IEEE 1149.1 Standard for Boundary Scan Test as the back plane test bus. Analog test busses are provided to support the IEEE 1149.4 Mixed-Signal test standard. The IEEE1532 Standard for In-System Programmability (ISP), which utilizes 1149.1 for communication and control, is also supported.
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