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Main CompactRISC Architecture Benefits
- Minimal Die Size: Provides space for on-chip application specific peripherals and memory
- Small Code Size: Avoids typical code expansion of RISC processors
- High Performance: Delivers sufficient performance to meet most embedded application needs
- Reduces Power: Suitable for portable applications
- Design Flexibility: Uses a modular internal bus for interface to a variety of peripherals
- Proven Design: Used by National Semiconductor and other silicon providers over a range of processes
- Fully Synthesizable: Available through IPextreme, Inc. partner for Licensing.
- Established / Proven Development Tools
CompactRISC CR16CP Architecture
CompactRISC CR16CP FAQs
IPextreme Inc. Licensing Program
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Key Architectural Features
- 3-Stage Pipeline (Fetch - Decode - Execute)
- Variable Instruction Length (16, 32 or 48-bit Instruction Length)
- Two Operating Modes (User / Supervisor)
- Von-Neumann Bus Architecture, compliant to AMBATM 2.0
- Load/Store Unit (LSU)
- 16 x 8 bit Hardware Multiplier (16/32 bit Result)
- 32-bit Barrell Shifter
- Nexus5001 compliant On-chip Debug
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