LMK03806 Ultra-Low Jitter Clock Generator
The highly integrated clock generator features the industry's best jitter performance. Delivering 14 independently programmable ultra-low jitter outputs from a single low-cost crystal, the LMK03806 enables a dramatic reduction in component count up to 80% with PCB area and BOM cost reduction up to 50%.
Key Features
- Generates multiple clocks from a low cost crystal or external clock
- High-frequency VCO and programmable output dividers
- Sub-50 fs RMS jitter at 312.5 MHz
- Highly integrated solution
- Reduces board area
- Lowers BOM cost by up to 50%
- 14 outputs with programmable format (LVDS, LVPECL, LVCMOS)
- Programmable dividers to generate multiple clocks from a low-cost crystal
LMK04800 Family Clock Jitter Cleaners
Key Performance Specifications
- Ultra-low RMS jitter performance (Jitter Performance Demonstration Video)
- 111 fs RMS jitter (12 kHz to 20 MHz) at 184.32 MHz
- 123 fs RMS jitter (100 Hz to 20 MHz) at 184.32 MHz
- Dual-loop PLLatinum™ PLL architecture
- -162 dBc/Hz wideband noise floor
- -227dBc/Hz PLL figure of merit
- 1.536 GHz max output frequency
- 25 ps step analog delay control
Product Features
- Hold-over mode supports recovery of clock when input clock is lost
- Multiple clock inputs with automatic switching
- 50% duty cycle output dividers, 1 to 1045 (even and odd)
- 12 programmable outputs (LVPECL, LVDS, or LVCMOS)
- Precision digital and analog delays
- Zero-delay mode
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LMK00301 3-GHz, 10-Output Differential Fanout Buffer / Level Translator
The LMK00301 differential fanout buffer/level translator accepts a single-ended, differential, or crystal input, and produces 10 buffered copies up to 3 GHz in LVDS, LVPECL, or HCSL format.
- 3:1 input multiplexer
- Two differential inputs accept DC-coupled LVPECL, LVDS, CML, SSTL, HSTL and single-ended clocks
- Differential input operates from DC to 3.1 GHz
- One crystal input accepts a 10 to 40 MHz crystal or single-ended clock
- Two banks with 5 differential outputs each
- Selectable output type (per bank): LVPECL, LVDS, HCSL, or Hi-Z
- 51 fs RMS additive jitter for LVPECL at 156.25 MHz (12 kHz – 20 MHz) with clock source
- LVCMOS output with synchronous enable input
- Pin-controlled configuration
LMX2541 Family PLL+VCO
World's Lowest Noise Integrated Frequency Synthesizer
The LMX2541 family is the world's lowest noise integrated frequency synthesizer. Featuring the world's lowest noise phase-locked loop (PLL) with bypass-able integrated VCO, the LMX2541 provides less than 2 milli-radians (mrad) root-mean-square (RMS) noise at 2.1 GHz and 3.5 mrad RMS noise at 3.5 GHz, outperforming the nearest competitor by 10 dB in both in-band PLL noise and spurious performance.
- Normalized PLL phase noise of -225 dBc/Hz
- Ultra-low RMS noise and spurs
- Wide frequency range 31.6 MHz to 4 GHz
- Internal VCO can be bypassed for use with external VCO
The LMX2541 is well-suited for local oscillator (LO) applications in next-generation basestation radio transceivers such as Long-Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), and multi-standard radios. When paired with the LMK04000 clock jitter cleaner, the LMX2541 significantly improves system error vector magnitude (EVM), resulting in enhanced receiver sensitivity and transmitter spectral purity.
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