Clock & Timing Solutions

Analog University Courses

Fundamentals

• Phase Noise & Jitter Basics and Clock Jitter Cleaning Using the LMK Family
• Advantages and Pitfalls of Using Fractional N PLLs

Advanced

• Topics in Precision Timing and Clock Conditioning
• The Impact of Various PLL Parameters on System Performance

Clock Design Tool Software

• Getting Started (Part 1)
• Loop Filter Design (Part 2)
• Device Simulation (Part 3)

Product Webinars

• LMX2541 Integrated PLLatinum PLL+VCO
  • Features & Performance Overview (Part 1)
  • Eval Board Hookup (Part 2)
  • Phase Noise (Part 3)
  • Fractional Spurs (Part 4)
  • Simulation Using National's Clock Design Tool (Part 5)
• Low Noise Frequency Synthesizers (July 2009)
• Understanding Fractional N-PLL (December 2008)
• Energy Saving, High Performance 3G-SDI Solutions (July 2008)
  
• Local Oscillator Characteristics & Design Considerations (April 2008)
  

Documents

Handbooks

• PLL Performance, Simulation and Design Handbook (4^th Ed)
• Clock Conditioner Owner's Manual (pdf 3.7MB)
• LVDS Owner's Manual (4^th Ed)

PLL Fundamentals New!

• Part 1) PLL Building Blocks (pdf)
• Part 2) PLL Behavior (pdf)
• Part 3) PLL Design (pdf)
• Part 4) PLL in Clocking Applications (pdf)
• Note: Most pages in these PDFs contain speaker notes in the upper left corner

App Notes

• AN-1939: Crystal Based Oscillator Design with the LMK04000 Family
• AN-1910: LMK04000 Family Phase Noise Characterization
• AN-1879: Fractional N Frequency Synthesis
• AN-1865: Frequency Synthesis and Planning for PLL Architectures
• AN-1864: Phase Synchronization with Multiple Devices and Frequencies
• AN-1821: CPRI Repeater System
• AN-1734: Using the LMK03000C to Clean Recovered Clocks
• AN-1558: Clocking High-Speed A/D Converters
• AN-1503: Designing an ATCA Compliant M-LVDS Clock Distribution Network
• AN-1275: Optimizing LMX243x Input Sensitivity Using Simple Matching Techniques
• AN-1173: High Speed BUS LVDS Clock Distribution Using the DS92CK16 Clock Distribution Device
• AN-1098: Loading PLL Frequency Synthesizers with COP8 Microcontrollers
• AN-1052: Noise Floor Measurement of PLL Frequency Synthesizers
• AN-1006: Phase-Locked Loop Based Clock Generators
• AN-1001: An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL's
• AN-1000: A Fast Locking Scheme for PLL Frequency Synthesizers
• AN-884: Integrated LNA and Mixer
  Basics
• AB-125: Delta Sigma PLLs Raise The Standard For Performance
• The Impact of Various PLL Parameters on System Performance