-- Generated by boundaryScanGenerate 4.2-Build20040928.017 on 12/11/06 10:09:53 -- BSDL Version 2001 entity phyter_hp is generic (PHYSICAL_PIN_MAP : string := "DEFAULT_PACKAGE_NAME"); port ( -- Port List TPRDM : linkage bit; TPRDP : linkage bit; CDVSS1 : linkage bit; CDVSS2 : linkage bit; TPTDM : linkage bit; TPTDP : linkage bit; ANA18VDD : linkage bit; ANA18VSS1 : linkage bit; ANA18VSS2 : linkage bit; ANA33VDD : linkage bit; REG_OUT : linkage bit; VREF : linkage bit; GPIO1 : inout bit; GPIO2 : inout bit; GPIO3 : inout bit; CLK2MAC : inout bit; GPIO4 : inout bit; LED_ACT : inout bit; LED_SPD : inout bit; LED_LNK : inout bit; RESET_N : in bit; MDIO : inout bit; MDC : in bit; IO_VDD2 : linkage bit; X2 : linkage bit; X1 : linkage bit; IO_VSS2 : linkage bit; CORE_VSS : linkage bit; GPIO8 : inout bit; GPIO9 : inout bit; RX_CLK : inout bit; RX_DV : inout bit; CRS : inout bit; RX_ER : inout bit; COL : inout bit; RXD_3 : inout bit; RXD_2 : inout bit; RXD_1 : inout bit; RXD_0 : inout bit; EN_1588 : linkage bit; IO_VSS1 : linkage bit; IO_VDD1 : linkage bit; TX_CLK : inout bit; TX_EN : inout bit; TXD_0 : inout bit; TXD_1 : inout bit; TXD_2 : inout bit; TXD_3 : inout bit; PWRDN_INTN : inout bit; TCK : in bit; TDO : out bit; TMS : in bit; TRST_N : in bit; TDI : in bit); use STD_1149_1_2001.all; use LVS_BSCAN_CELLS.all; attribute COMPONENT_CONFORMANCE of phyter_hp: entity is "STD_1149_1_2001"; --Pin mappings attribute PIN_MAP of phyter_hp: entity is PHYSICAL_PIN_MAP; constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING := "TPRDM : 13 , " & "TPRDP : 14 , " & "CDVSS1 : 15 , " & "CDVSS2 : 99 , " & "TPTDM : 16 , " & "TPTDP : 17 , " & "ANA18VDD : 98 , " & "ANA18VSS1 : 18 , " & "ANA18VSS2 : 97 , " & "ANA33VDD : 19 , " & "REG_OUT : 96 , " & "VREF : 20 , " & "GPIO1 : 21 , " & "GPIO2 : 22 , " & "GPIO3 : 23 , " & "CLK2MAC : 24 , " & "GPIO4 : 25 , " & "LED_ACT : 26 , " & "LED_SPD : 27 , " & "LED_LNK : 28 , " & "RESET_N : 29 , " & "MDIO : 30 , " & "MDC : 31 , " & "IO_VDD2 : 32 , " & "X2 : 33 , " & "X1 : 34 , " & "IO_VSS2 : 35 , " & "CORE_VSS : 95 , " & "GPIO8 : 36 , " & "GPIO9 : 37 , " & "RX_CLK : 38 , " & "RX_DV : 39 , " & "CRS : 40 , " & "RX_ER : 41 , " & "COL : 42 , " & "RXD_3 : 43 , " & "RXD_2 : 44 , " & "RXD_1 : 45 , " & "RXD_0 : 46 , " & "EN_1588 : 47 , " & "IO_VSS1 : 48 , " & "IO_VDD1 : 49 , " & "TX_CLK : 1 , " & "TX_EN : 2 , " & "TXD_0 : 3 , " & "TXD_1 : 4 , " & "TXD_2 : 5 , " & "TXD_3 : 6 , " & "PWRDN_INTN : 7 , " & "TCK : 8 , " & "TDO : 9 , " & "TMS : 10 , " & "TRST_N : 11 , " & "TDI : 12 " ; attribute TAP_SCAN_RESET of TRST_N : signal is true; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH); attribute INSTRUCTION_LENGTH of phyter_hp: entity is 5; attribute INSTRUCTION_OPCODE of phyter_hp: entity is "IDCODE (11110)," & "BYPASS (11111)," & "EXTEST (11001)," & "SAMPLE (11000)," & "PRELOAD (11000)," & "HIGHZ (11011) " ; attribute INSTRUCTION_CAPTURE of phyter_hp: entity is "xxx01"; attribute IDCODE_REGISTER of phyter_hp: entity is "0000" & -- version "1000000000110000" & -- part number "00000001111" & -- manufacturer's identity "1"; -- required by 1149.1 attribute REGISTER_ACCESS of phyter_hp: entity is "BOUNDARY ( SAMPLE, PRELOAD )," & "BYPASS (HIGHZ) " ; --Boundary scan definition attribute BOUNDARY_LENGTH of phyter_hp: entity is 56; attribute BOUNDARY_REGISTER of phyter_hp: entity is -- num cell port function safe [ccell disval rslt] " 55 (BC_2 , * , control , 0 ) ,"& " 54 (LV_BC_7 , GPIO1 , bidir , X , 55 , 0 , Z ),"& " 53 (BC_2 , * , control , 0 ) ,"& " 52 (LV_BC_7 , GPIO2 , bidir , X , 53 , 0 , Z ),"& " 51 (BC_2 , * , control , 0 ) ,"& " 50 (LV_BC_7 , GPIO3 , bidir , X , 51 , 0 , Z ),"& " 49 (BC_2 , * , control , 0 ) ,"& " 48 (LV_BC_7 , CLK2MAC , bidir , X , 49 , 0 , Z ),"& " 47 (BC_2 , * , control , 0 ) ,"& " 46 (LV_BC_7 , GPIO4 , bidir , X , 47 , 0 , Z ),"& " 45 (BC_2 , * , control , 0 ) ,"& " 44 (LV_BC_7 , LED_ACT , bidir , X , 45 , 0 , Z ),"& " 43 (BC_2 , * , control , 0 ) ,"& " 42 (LV_BC_7 , LED_SPD , bidir , X , 43 , 0 , Z ),"& " 41 (BC_2 , * , control , 0 ) ,"& " 40 (LV_BC_7 , LED_LNK , bidir , X , 41 , 0 , Z ),"& " 39 (BC_2 , RESET_N , input , X ) ,"& " 38 (BC_2 , * , control , 0 ) ,"& " 37 (LV_BC_7 , MDIO , bidir , X , 38 , 0 , Z ),"& " 36 (BC_2 , MDC , input , X ) ,"& " 35 (BC_2 , * , control , 0 ) ,"& " 34 (LV_BC_7 , GPIO8 , bidir , X , 35 , 0 , Z ),"& " 33 (BC_2 , * , control , 0 ) ,"& " 32 (LV_BC_7 , GPIO9 , bidir , X , 33 , 0 , Z ),"& " 31 (BC_2 , * , control , 0 ) ,"& " 30 (LV_BC_7 , RX_CLK , bidir , X , 31 , 0 , Z ),"& " 29 (BC_2 , * , control , 0 ) ,"& " 28 (LV_BC_7 , RX_DV , bidir , X , 29 , 0 , Z ),"& " 27 (BC_2 , * , control , 0 ) ,"& " 26 (LV_BC_7 , CRS , bidir , X , 27 , 0 , Z ),"& " 25 (BC_2 , * , control , 0 ) ,"& " 24 (LV_BC_7 , RX_ER , bidir , X , 25 , 0 , Z ),"& " 23 (BC_2 , * , control , 0 ) ,"& " 22 (LV_BC_7 , COL , bidir , X , 23 , 0 , Z ),"& " 21 (BC_2 , * , control , 0 ) ,"& " 20 (LV_BC_7 , RXD_3 , bidir , X , 21 , 0 , Z ),"& " 19 (BC_2 , * , control , 0 ) ,"& " 18 (LV_BC_7 , RXD_2 , bidir , X , 19 , 0 , Z ),"& " 17 (BC_2 , * , control , 0 ) ,"& " 16 (LV_BC_7 , RXD_1 , bidir , X , 17 , 0 , Z ),"& " 15 (BC_2 , * , control , 0 ) ,"& " 14 (LV_BC_7 , RXD_0 , bidir , X , 15 , 0 , Z ),"& " 13 (BC_2 , * , control , 0 ) ,"& " 12 (LV_BC_7 , TX_CLK , bidir , X , 13 , 0 , Z ),"& " 11 (BC_2 , * , control , 0 ) ,"& " 10 (LV_BC_7 , TX_EN , bidir , X , 11 , 0 , Z ),"& " 9 (BC_2 , * , control , 0 ) ,"& " 8 (LV_BC_7 , TXD_0 , bidir , X , 9 , 0 , Z ),"& " 7 (BC_2 , * , control , 0 ) ,"& " 6 (LV_BC_7 , TXD_1 , bidir , X , 7 , 0 , Z ),"& " 5 (BC_2 , * , control , 0 ) ,"& " 4 (LV_BC_7 , TXD_2 , bidir , X , 5 , 0 , Z ),"& " 3 (BC_2 , * , control , 0 ) ,"& " 2 (LV_BC_7 , TXD_3 , bidir , X , 3 , 0 , Z ),"& " 1 (BC_2 , * , control , 0 ) ,"& " 0 (LV_BC_7 , PWRDN_INTN , bidir , X , 1 , 0 , Z ) "; end phyter_hp;