-- Generated by boundaryScanGenerate 3.3c-Build20010123.006 on 05/29/01 13:36:46 -- BSDL Version 1994 entity DP83865 is generic (PHYSICAL_PIN_MAP : string := "DEFAULT_PACKAGE_NAME"); port ( -- Port List NON_IEEE_STRAP : inout bit; RESERVED1 : inout bit; INTERRUPT_N : inout bit; IO_VDD1 : linkage bit; VSS1 : linkage bit; MAN_MDIX_STRAP : inout bit; SPEED0_STRAP : inout bit; SPEED1_STRAP : inout bit; DUPLEX_STRAP : inout bit; AN_EN_STRAP : inout bit; CORE_VDD1 : linkage bit; VSS2 : linkage bit; PHYADDR0_STRAP : inout bit; PHYADDR1_STRAP : inout bit; IO_VDD2 : linkage bit; VSS3 : linkage bit; PHYADDR2_STRAP : inout bit; PHYADDR3_STRAP : inout bit; CORE_VDD2 : linkage bit; VSS4 : linkage bit; IO_VDD3 : linkage bit; VSS5 : linkage bit; RESERVED2 : in bit; TCK : in bit; CORE_VDD3 : linkage bit; VSS6 : linkage bit; TMS : in bit; TDO : out bit; IO_VDD4 : linkage bit; VSS7 : linkage bit; TDI : in bit; TRST_N : in bit; RESET_N : in bit; VDD_SEL : linkage bit; CORE_VDD4 : linkage bit; VSS8 : linkage bit; IO_VDD5 : linkage bit; VSS9 : linkage bit; COL : inout bit; CRS : inout bit; RX_ER : inout bit; IO_VDD6 : linkage bit; VSS10 : linkage bit; RX_DV : inout bit; RXD7 : inout bit; RXD6 : inout bit; RXD5 : inout bit; CORE_VDD5 : linkage bit; VSS11 : linkage bit; RXD4 : inout bit; RXD3 : inout bit; RXD2 : inout bit; IO_VDD7 : linkage bit; VSS12 : linkage bit; RXD1 : inout bit; RXD0 : inout bit; RX_CLK : inout bit; IO_VDD8 : linkage bit; VSS13 : linkage bit; TX_CLK : inout bit; TX_ER : inout bit; TX_EN : inout bit; CORE_VDD6 : linkage bit; VSS14 : linkage bit; TXD7 : inout bit; TXD6 : inout bit; TXD5 : inout bit; TXD4 : inout bit; IO_VDD9 : linkage bit; VSS15 : linkage bit; TXD3 : inout bit; TXD2 : inout bit; CORE_VDD7 : linkage bit; VSS16 : linkage bit; TXD1 : inout bit; TXD0 : inout bit; IO_VDD10 : linkage bit; VSS17 : linkage bit; GTX_CLK : in bit; MDIO : inout bit; MDC : in bit; VSS18 : linkage bit; IO_VDD11 : linkage bit; RESERVED3 : in bit; CLK_TO_MAC : inout bit; CLOCK_IN : in bit; CLOCK_OUT : linkage bit; MAC_CLK_EN_STRAP : inout bit; MDIX_EN_STRAP : inout bit; IO_VDD12 : linkage bit; VSS19 : linkage bit; CORE_VDD8 : linkage bit; VSS20 : linkage bit; MULTI_EN_STRAP : inout bit; PHYADDR4_STRAP : inout bit; V25_AVDD2 : linkage bit; VSS21 : linkage bit; V18_AVDD2 : linkage bit; VSS22 : linkage bit; CORE_VDD9 : linkage bit; V25_AVDD1 : linkage bit; BG_REF : linkage bit; V18_AVDD1_1 : linkage bit; VSS23 : linkage bit; V18_AVDD1_2 : linkage bit; VSS24 : linkage bit; VSS25 : linkage bit; MDIA_P : linkage bit; MDIA_N : linkage bit; VSS26 : linkage bit; V18_AVDD1_3 : linkage bit; VSS27 : linkage bit; VSS28 : linkage bit; MDIB_P : linkage bit; MDIB_N : linkage bit; VSS29 : linkage bit; V18_AVDD1_4 : linkage bit; VSS30 : linkage bit; VSS31 : linkage bit; MDIC_P : linkage bit; MDIC_N : linkage bit; VSS32 : linkage bit; V18_AVDD1_5 : linkage bit; VSS33 : linkage bit; VSS34 : linkage bit; MDID_P : linkage bit; MDID_N : linkage bit; VSS35 : linkage bit); use STD_1149_1_1994.all; use LVS_BSCAN_CELLS.all; attribute COMPONENT_CONFORMANCE of DP83865: entity is "STD_1149_1_1993"; --Pin mappings attribute PIN_MAP of DP83865: entity is PHYSICAL_PIN_MAP; constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING := "NON_IEEE_STRAP : 1 , " & "RESERVED1 : 2 , " & "INTERRUPT_N : 3 , " & "IO_VDD1 : 4 , " & "VSS1 : 5 , " & "MAN_MDIX_STRAP : 6 , " & "SPEED0_STRAP : 7 , " & "SPEED1_STRAP : 8 , " & "DUPLEX_STRAP : 9 , " & "AN_EN_STRAP : 10 , " & "CORE_VDD1 : 11 , " & "VSS2 : 12 , " & "PHYADDR0_STRAP : 13 , " & "PHYADDR1_STRAP : 14 , " & "IO_VDD2 : 15 , " & "VSS3 : 16 , " & "PHYADDR2_STRAP : 17 , " & "PHYADDR3_STRAP : 18 , " & "CORE_VDD2 : 19 , " & "VSS4 : 20 , " & "IO_VDD3 : 21 , " & "VSS5 : 22 , " & "RESERVED2 : 23 , " & "TCK : 24 , " & "CORE_VDD3 : 25 , " & "VSS6 : 26 , " & "TMS : 27 , " & "TDO : 28 , " & "IO_VDD4 : 29 , " & "VSS7 : 30 , " & "TDI : 31 , " & "TRST_N : 32 , " & "RESET_N : 33 , " & "VDD_SEL : 34 , " & "CORE_VDD4 : 35 , " & "VSS8 : 36 , " & "IO_VDD5 : 37 , " & "VSS9 : 38 , " & "COL : 39 , " & "CRS : 40 , " & "RX_ER : 41 , " & "IO_VDD6 : 42 , " & "VSS10 : 43 , " & "RX_DV : 44 , " & "RXD7 : 45 , " & "RXD6 : 46 , " & "RXD5 : 47 , " & "CORE_VDD5 : 48 , " & "VSS11 : 49 , " & "RXD4 : 50 , " & "RXD3 : 51 , " & "RXD2 : 52 , " & "IO_VDD7 : 53 , " & "VSS12 : 54 , " & "RXD1 : 55 , " & "RXD0 : 56 , " & "RX_CLK : 57 , " & "IO_VDD8 : 58 , " & "VSS13 : 59 , " & "TX_CLK : 60 , " & "TX_ER : 61 , " & "TX_EN : 62 , " & "CORE_VDD6 : 63 , " & "VSS14 : 64 , " & "TXD7 : 65 , " & "TXD6 : 66 , " & "TXD5 : 67 , " & "TXD4 : 68 , " & "IO_VDD9 : 69 , " & "VSS15 : 70 , " & "TXD3 : 71 , " & "TXD2 : 72 , " & "CORE_VDD7 : 73 , " & "VSS16 : 74 , " & "TXD1 : 75 , " & "TXD0 : 76 , " & "IO_VDD10 : 77 , " & "VSS17 : 78 , " & "GTX_CLK : 79 , " & "MDIO : 80 , " & "MDC : 81 , " & "VSS18 : 82 , " & "IO_VDD11 : 83 , " & "RESERVED3 : 84 , " & "CLK_TO_MAC : 85 , " & "CLOCK_IN : 86 , " & "CLOCK_OUT : 87 , " & "MAC_CLK_EN_STRAP : 88 , " & "MDIX_EN_STRAP : 89 , " & "IO_VDD12 : 90 , " & "VSS19 : 91 , " & "CORE_VDD8 : 92 , " & "VSS20 : 93 , " & "MULTI_EN_STRAP : 94 , " & "PHYADDR4_STRAP : 95 , " & "V25_AVDD2 : 96 , " & "VSS21 : 97 , " & "V18_AVDD2 : 98 , " & "VSS22 : 99 , " & "CORE_VDD9 : 100 , " & "V25_AVDD1 : 101 , " & "BG_REF : 102 , " & "V18_AVDD1_1 : 103 , " & "VSS23 : 104 , " & "V18_AVDD1_2 : 105 , " & "VSS24 : 106 , " & "VSS25 : 107 , " & "MDIA_P : 108 , " & "MDIA_N : 109 , " & "VSS26 : 110 , " & "V18_AVDD1_3 : 111 , " & "VSS27 : 112 , " & "VSS28 : 113 , " & "MDIB_P : 114 , " & "MDIB_N : 115 , " & "VSS29 : 116 , " & "V18_AVDD1_4 : 117 , " & "VSS30 : 118 , " & "VSS31 : 119 , " & "MDIC_P : 120 , " & "MDIC_N : 121 , " & "VSS32 : 122 , " & "V18_AVDD1_5 : 123 , " & "VSS33 : 124 , " & "VSS34 : 125 , " & "MDID_P : 126 , " & "MDID_N : 127 , " & "VSS35 : 128 " ; attribute TAP_SCAN_RESET of TRST_N : signal is true; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH); attribute INSTRUCTION_LENGTH of DP83865: entity is 32; attribute INSTRUCTION_OPCODE of DP83865: entity is "IDCODE (11111111111111111111111111111110)," & "BYPASS (11111111111111111111111111111111)," & "EXTEST (00000000000000000000000000000000, 11111111111111111111111111101000)," & "SAMPLE (11111111111111111111111111111000)," & "HIGHZ (11111111111111111111111111001111)," & "CLAMP (11111111111111111111111111101111) " ; attribute INSTRUCTION_CAPTURE of DP83865: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01"; attribute IDCODE_REGISTER of DP83865: entity is "0000" & -- version "0000000000000111" & -- part number "00000011111" & -- manufacturer's identity "1"; -- required by 1149.1 attribute REGISTER_ACCESS of DP83865: entity is "BYPASS (HIGHZ, CLAMP) " ; --Boundary scan definition attribute BOUNDARY_LENGTH of DP83865: entity is 90; attribute BOUNDARY_REGISTER of DP83865: entity is -- num cell port function safe [ccell disval rslt] " 89 (BC_2 , * , control , 0 ) ,"& " 88 (LV_BC_7 , NON_IEEE_STRAP , bidir , X , 89 , 0 , Z ),"& " 87 (BC_2 , * , control , 0 ) ,"& " 86 (LV_BC_7 , RESERVED1 , bidir , X , 87 , 0 , Z ),"& " 85 (BC_2 , * , control , 0 ) ,"& " 84 (LV_BC_7 , INTERRUPT_N , bidir , X , 85 , 0 , Z ),"& " 83 (BC_2 , * , control , 0 ) ,"& " 82 (LV_BC_7 , MAN_MDIX_STRAP , bidir , X , 83 , 0 , Z ),"& " 81 (BC_2 , * , control , 0 ) ,"& " 80 (LV_BC_7 , SPEED0_STRAP , bidir , X , 81 , 0 , Z ),"& " 79 (BC_2 , * , control , 0 ) ,"& " 78 (LV_BC_7 , SPEED1_STRAP , bidir , X , 79 , 0 , Z ),"& " 77 (BC_2 , * , control , 0 ) ,"& " 76 (LV_BC_7 , DUPLEX_STRAP , bidir , X , 77 , 0 , Z ),"& " 75 (BC_2 , * , control , 0 ) ,"& " 74 (LV_BC_7 , AN_EN_STRAP , bidir , X , 75 , 0 , Z ),"& " 73 (BC_2 , * , control , 0 ) ,"& " 72 (LV_BC_7 , PHYADDR0_STRAP , bidir , X , 73 , 0 , Z ),"& " 71 (BC_2 , * , control , 0 ) ,"& " 70 (LV_BC_7 , PHYADDR1_STRAP , bidir , X , 71 , 0 , Z ),"& " 69 (BC_2 , * , control , 0 ) ,"& " 68 (LV_BC_7 , PHYADDR2_STRAP , bidir , X , 69 , 0 , Z ),"& " 67 (BC_2 , * , control , 0 ) ,"& " 66 (LV_BC_7 , PHYADDR3_STRAP , bidir , X , 67 , 0 , Z ),"& " 65 (LV_BC_7 , RESERVED2 , input , X ),"& " 64 (LV_BC_7 , RESET_N , input , X ),"& " 63 (BC_2 , * , control , 0 ) ,"& " 62 (LV_BC_7 , COL , bidir , X , 63 , 0 , Z ),"& " 61 (BC_2 , * , control , 0 ) ,"& " 60 (LV_BC_7 , CRS , bidir , X , 61 , 0 , Z ),"& " 59 (BC_2 , * , control , 0 ) ,"& " 58 (LV_BC_7 , RX_ER , bidir , X , 59 , 0 , Z ),"& " 57 (BC_2 , * , control , 0 ) ,"& " 56 (LV_BC_7 , RX_DV , bidir , X , 57 , 0 , Z ),"& " 55 (BC_2 , * , control , 0 ) ,"& " 54 (LV_BC_7 , RXD7 , bidir , X , 55 , 0 , Z ),"& " 53 (BC_2 , * , control , 0 ) ,"& " 52 (LV_BC_7 , RXD6 , bidir , X , 53 , 0 , Z ),"& " 51 (BC_2 , * , control , 0 ) ,"& " 50 (LV_BC_7 , RXD5 , bidir , X , 51 , 0 , Z ),"& " 49 (BC_2 , * , control , 0 ) ,"& " 48 (LV_BC_7 , RXD4 , bidir , X , 49 , 0 , Z ),"& " 47 (BC_2 , * , control , 0 ) ,"& " 46 (LV_BC_7 , RXD3 , bidir , X , 47 , 0 , Z ),"& " 45 (BC_2 , * , control , 0 ) ,"& " 44 (LV_BC_7 , RXD2 , bidir , X , 45 , 0 , Z ),"& " 43 (BC_2 , * , control , 0 ) ,"& " 42 (LV_BC_7 , RXD1 , bidir , X , 43 , 0 , Z ),"& " 41 (BC_2 , * , control , 0 ) ,"& " 40 (LV_BC_7 , RXD0 , bidir , X , 41 , 0 , Z ),"& " 39 (BC_2 , * , control , 0 ) ,"& " 38 (LV_BC_7 , RX_CLK , bidir , X , 39 , 0 , Z ),"& " 37 (BC_2 , * , control , 0 ) ,"& " 36 (LV_BC_7 , TX_CLK , bidir , X , 37 , 0 , Z ),"& " 35 (BC_2 , * , control , 0 ) ,"& " 34 (LV_BC_7 , TX_ER , bidir , X , 35 , 0 , Z ),"& " 33 (BC_2 , * , control , 0 ) ,"& " 32 (LV_BC_7 , TX_EN , bidir , X , 33 , 0 , Z ),"& " 31 (BC_2 , * , control , 0 ) ,"& " 30 (LV_BC_7 , TXD7 , bidir , X , 31 , 0 , Z ),"& " 29 (BC_2 , * , control , 0 ) ,"& " 28 (LV_BC_7 , TXD6 , bidir , X , 29 , 0 , Z ),"& " 27 (BC_2 , * , control , 0 ) ,"& " 26 (LV_BC_7 , TXD5 , bidir , X , 27 , 0 , Z ),"& " 25 (BC_2 , * , control , 0 ) ,"& " 24 (LV_BC_7 , TXD4 , bidir , X , 25 , 0 , Z ),"& " 23 (BC_2 , * , control , 0 ) ,"& " 22 (LV_BC_7 , TXD3 , bidir , X , 23 , 0 , Z ),"& " 21 (BC_2 , * , control , 0 ) ,"& " 20 (LV_BC_7 , TXD2 , bidir , X , 21 , 0 , Z ),"& " 19 (BC_2 , * , control , 0 ) ,"& " 18 (LV_BC_7 , TXD1 , bidir , X , 19 , 0 , Z ),"& " 17 (BC_2 , * , control , 0 ) ,"& " 16 (LV_BC_7 , TXD0 , bidir , X , 17 , 0 , Z ),"& " 15 (LV_BC_7 , GTX_CLK , input , X ),"& " 14 (BC_2 , * , control , 0 ) ,"& " 13 (LV_BC_7 , MDIO , bidir , X , 14 , 0 , Z ),"& " 12 (LV_BC_7 , MDC , input , X ),"& " 11 (LV_BC_7 , RESERVED3 , input , X ),"& " 10 (BC_2 , * , control , 0 ) ,"& " 9 (LV_BC_7 , CLK_TO_MAC , bidir , X , 10 , 0 , Z ),"& " 8 (BC_4 , CLOCK_IN , clock , X ) ,"& " 7 (BC_2 , * , control , 0 ) ,"& " 6 (LV_BC_7 , MAC_CLK_EN_STRAP , bidir , X , 7 , 0 , Z ),"& " 5 (BC_2 , * , control , 0 ) ,"& " 4 (LV_BC_7 , MDIX_EN_STRAP , bidir , X , 5 , 0 , Z ),"& " 3 (BC_2 , * , control , 0 ) ,"& " 2 (LV_BC_7 , MULTI_EN_STRAP , bidir , X , 3 , 0 , Z ),"& " 1 (BC_2 , * , control , 0 ) ,"& " 0 (LV_BC_7 , PHYADDR4_STRAP , bidir , X , 1 , 0 , Z ) "; end DP83865;