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EOS/ESD INFORMATION

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  Junction Damage:

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Optical photo of junction damage. Optical photo of junction damage. SEM photo of junction damage.
SEM photo of junction damage. Optical photo of junction damage.
 
  • Effect "What does it look like?"
    • May take on the appearance of oxide defects
      • Maybe nothing visible, but causes an electrical fault
      • Damage visible after deprocessing
    • Optical inspection: silvery, whitish or faint line between two die-level

  • Causes (What caused the damage?)
    • Voltage spikes
      • Diagram or refer to HBM waveform  or other waveforms
      • Greater than 500V and less than 100 (µsec pulse width)
        • Reference: Intel web site (www.intel.com)
      • Pulse width between 200 nsec and 2msec
        • Ref: Smith, J.S., "Electrical Overstress Damage in Microcircuits", RADC #11.

  • Sources (What generated the voltage spike)
    • Humans
      • Handling by un-grounded personnel
        • Insufficient training or certificate program
        • Uncontrolled work flows / processes
        • Current procedures or practices not ESD compliant

    • Machine
      • Design
        • Inherent weakness in design (layout or circuit)
      • Improperly grounded
        • All components contacting IC or PCBs must be conductive and connected to ground
        • All components contacting IC or PCBs must be conductive and equi-potential to ground (ie. Phenolic spacers in a handler; Suspect any non-metallic piece
        • Soldering Irons (ie. Too high resistance of tip to ground; Three prong electrical plug).
      • Ground bounce sources
        • Switching relays
      • Field Inductance or EMI
        • Arcing; CRT related items; Electric motors; Microwave sources, RF sources

    • Cleanliness of raw power
      • Noisy supply from external
        • Monitor Electric utility
      • Network load variations
        • Ground bounce sources; Voltage supply harmonics; Switching relays

    • Environment
      • Weather
        • Lightning strikes; Low humidity (<40RH)
      • Triboelectric materials
        • Non-conductive table tops, wall panels, floor. Packing & transport materials. Styrofoam coffee cups.
      • Resistive ground references
        • ESD ground common with facility ground

    • Manufacturing defects
      • Inherent design weakness
        • circuit design; layout
      • Silicon defect
        • crystalline; particulates

  • Methods for Investigation
    • Look first at
      • Quantify scope/size of problem
        • Is it a sporadic occurrence?
        • Does it happen on a recurring basis?
        • Does it appear to be "batch" related?
      • Most likely problem areas
        • Is there adequate ESD training?
        • Are ESD control components maintained?
        • Are there unwanted voltage spikes in Electrical Test?
        • Are the machines properly grounded?
      • Did any of the following occur?
        • Non-standard process handling (ie. re-work, off-line sampling)
        • Process or material changes prior to recent events (ie. ESD component or raw material changes; Power disruptions to plant or assembly line)

    • Didn't find anything. Now What?
      • Address any findings resulting from ESD survey or process review
        • ESD audit using spec: EIA 625
        • Humidity survey (>40%RH)
        • Grounding (human and machine)
        • Packing materials
        • Remove non-essential ESD-generating material
        • ESD or static field sources
        • Check application for inductors in proximity
        • Supply line monitors

    • Found something. Now what?
      • ESD Survey