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In a high speed digital system the ability to reduce "switching noise" is critical for the proper functioning of the system. Switching noise can be thought of as any disturbance that erodes either the logic "1" or logic "0" levels. Digital devices are designed with built in noise margins. Noise margin is the difference between worst case output signal level from a driver and the minimum signal necessary to insure that an input always makes a correct determination of the logic state being transmitted. Since all the signals on a device are referenced to the device/system ground potential, it is critical that this ground potential be maintained. Two factors that influence the stability of the ground potential are the amount of current per unit time flowing into ground and the inductance of the device ground lead(s).
While the amount of current per unit time flowing into ground is determined by the design of the device, lead inductance is a function of the packaging technology. Direct Chip Attach (Flip-Chip and Chip-On-Board) provides system designers with a low inductance option.
Inductance is a characteristic of a storage device that resists a change in current. In this case, the storage device is the ground lead of the IC. The unit for inductance is a Henry. Inductances associated with the digital IC world are usually in the nano-Henry (10-9 Henry) range. The interaction between the current flowing per unit time and the inductance of the device ground lead results in a voltage being developed.
This noise voltage potential (VN) developed across the inductance (L) due to the current per unit time (di/dt) flowing through the inductance can be calculated by:
VN = L di/dt (Eq. 1.)
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A simple analysis of a CMOS output driver (Fig. 1) will illustrate this effect. With the output, VOUT, switching from HIGH to LOW (VIN switching LOW to HIGH) the pulldown transistor would be ON and sinking current to system ground through the device ground lead. Assuming a large capacitive load (100pF) and a fast edge rate (1ns) on VIN for this output driver, VOUT would equal VDD (5V) during the transition time.
Rewriting Eq. 1:
VN = L * (IMAX/T) (Eq. 2.)
where
IMAX = K(VIN-VT)2/2 (Eq. 3)
VT is threshold voltage and K is a function of the device geometry and fabrication process. Letting K = 21.4 x 10-3 Amps/V2, VIN = 5V, and VT = 1V, and substituting into Eq. 3, IMAX = 0.171 amps. Substituting IMAX into Eq. 2 and assuming T = 1 nanosecond:
VN = L (0.171 Amps/1ns) Eq. 4.
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Table 1. Calculated VN by Package
| Package |
L (nH) |
VN (Volt) |
| DIP |
12.0 |
2.05 |
| QFP |
7.0 |
1.119 |
| BGA |
5.0 |
0.86 |
| COB |
2.6 |
0.44 |
| µBGA |
2.1 |
0.36 |
| Flip-Chip |
<0.1 |
0.01 |
From Eq. 4 it can be seen that the noise generated is directly proportional to the inductance L. Table 1 lists lead inductances and calculated (per Eq. 4) noise voltages for some common packages and Direct Chip Attach (COB, Flip-Chip) technologies. Keep in mind that Eq. 4 is for one driver only. If multiple drivers are switching resulting in more current flowing through the device ground lead(s), the resulting noise voltage will increase. Since Flip-Chip has the shortest device lead (bump) and thus the lowest lead inductance versus other package technologies, one will get better system performance regarding switching noise by using this method of DCA versus other packaging options.
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