Clock & Timing Home - Clock Jitter Cleaners, PLLatinum PLLs & PLL+VCOs, and Low-Jitter Clock Distribution from National Semiconductor

Product Tables

Clock Jitter Cleaners

Clock Distributors

Phase-Locked Loops

Other Timing-Related Products

Featured Sites

PDF Selection Guides

Analog Product Guide (including jitter cleaner, PLL, and clock distribution selection tables)
Wireless Infrastructure
Professional & Broadcast Video Products
Industrial Solutions
And more...

	Documents Application Notes PLL Performance, Simulation and Design Handbook (4^th Ed) Clock Conditioner Owner's Manual (pdf 3.7MB)
	Boards Evaluation Boards LMK Clock Conditioner Eval Boards LMX PLLatinum™ PLL/VCO Eval Boards USB2UWIRE-IFACE - USB ↔ uWire Interface Board: USB connection from CodeLoader 4 software to LMX and LMK evaluation boards Signal Path Reference Designs
	Videos Video Center e-Learning at PowerWise Design University
	Software Configuration, Simulation, & Programming Software Tools CodeLoader Clock Design Tool EasyPLL IBIS Models: LMK01000 LMK01010 LMK01020 LMK03000 LMK03001

Featured Design Resources

Handbooks

App Notes

AN-1939: Crystal Based Oscillator Design with the LMK04000 Family
AN-1910: LMK04000 Family Phase Noise Characterization
AN-1879: Fractional N Frequency Synthesis
AN-1865: Frequency Synthesis and Planning for PLL Architectures
AN-1864: Phase Synchronization with Multiple Devices and Frequencies
AN-1821: CPRI Repeater System
AN-1734: Using the LMK03000C to Clean Recovered Clocks
AN-1558: Clocking High-Speed A/D Converters
AN-1503: Designing an ATCA Compliant M-LVDS Clock Distribution Network
AN-1275: Optimizing LMX243x Input Sensitivity Using Simple Matching Techniques
AN-1173: High Speed BUS LVDS Clock Distribution Using the DS92CK16 Clock Distribution Device
AN-1098: Loading PLL Frequency Synthesizers with COP8 Microcontrollers
AN-1052: Noise Floor Measurement of PLL Frequency Synthesizers
AN-1006: Phase-Locked Loop Based Clock Generators
AN-1001: An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL’s
AN-1000: A Fast Locking Scheme for PLL Frequency Synthesizers
AN-884: Integrated LNA and Mixer
Basics
AB-125: Delta Sigma PLLs Raise The Standard For Performance