PowerWise® High-Speed Amplifiers
- 2.5 GHz Ultra Linear Fully Differential Amplifier
- 1.5 GHz Fully Differential Amplifier
- 1.2 GHz Differential Driver
- Digital Variable Gain Amplifier
PowerWise® High-Speed A/D Converters
- 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter
- 8-Bit, 3 GSPS A/D Converter
- 14-Bit, 155 MSPS A/D Converter
- 14-Bit, 105 MSPS A/D Converter
PowerWise® Clock Conditioners
- LMK04000 Family - Clock Jitter Cleaners with Cascaded PLLatinum PLLs
- LMK01000 Family - < 30 fs High Performance Clock Buffer, Divider, and Distributor for Clocks up to 1.6 GHz
- LMK03000 Family - Clock Jitter Cleaners with Integrated VCO
- LMK02000 Family - Clock Jitter Cleaners for use with external VCXO
- Frequency Synthesizer System, Integrated VCO
The Signal-Path Designer® is published every other month, the Signal-Path Designer newsletter's feature articles cover signal-path design techniques:
The reference designs include ADCs, front-end amplifiers, timing components, and power supply regulation.
- ADC16DV160 - High-IF Sub-Sampling Receiver System
- ADC16V130 - Low Intermediate Frequency Receiver System
- ADC083000 - Lowest Power 8-bit 3 GSPS Data Acquisition System
- ADC14DS105 - Low Intermediate Frequency Receiver System
- ADC14V155 - High Intermediate Frequency Receiver System
WaveVision Data Acquisition and Analysis System
Test and evaluate A/D converters with National's easy-to-use WaveVision software, which supports National's latest ADC evaluation boards.
Challenges of clocking a high-definition world – Part I: foundational concepts
Clocks and jitter affect all aspects of system performance, including signal-to-noise ratio (SNR) and throughput; understanding and implementing today's ever-higher-speed clocks is crucial.
Challenges of clocking a high-definition world – Part II: A system applications perspective
Part II examines issues specific to communication systems that are evolving from multi-module, single channel architectures to single-module architectures. The article also shows how to analyze the impact of multiple, uncorrelated noise sources on overall SNR, relate this to clock jitter, and present an example that illustrates the different jitter requirements for different ADC resolutions.
Use in-the-loop gain control to extend dynamic range.
Modern communications systems are demanding more dynamic range than current analog-to-digital converters (ADCs) can support. One way to gain system dynamic range is to use a digitally-controlled variable gain amplifier (DVGA) with a high-speed, high-resolution ADC in a digitally-controlled AGC loop.
With less capital available for continuous system “upgrades”, new data center solutions must be space- and energy-efficient while supporting multi-faceted expansion to keep ahead of users’ data storage needs. Engineers are leveraging open industry standards like PCI Express (PCIe) and SAS/SATA to create efficient architectures that address current and future data center requirements. With only limited input and output signal conditioning written directly into these standards, hardware design has been constrained by cable and PCB attenuation of high-speed serial data. Even within a single rack of equipment, signals that remain on backplanes will exhibit losses beyond those detailed in the PCIe standard.
