Signal Path Solutions

PowerWise® High-Speed Amplifiers

• LMH6554
  2.5 GHz Ultra Linear Fully Differential Amplifier
• LMH6552
  1.5 GHz Fully Differential Amplifier
• LMH6555
  1.2 GHz Differential Driver
• LMH6515
  Digital Variable Gain Amplifier

PowerWise® High-Speed A/D Converters

• ADC10D1000
  10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter
• ADC083000
  8-Bit, 3 GSPS A/D Converter
• ADC14V155
  14-Bit, 155 MSPS A/D Converter
• ADC14DS105
  14-Bit, 105 MSPS A/D Converter

PowerWise® Clock Conditioners

• LMK04000 Family - Clock Jitter Cleaners with Cascaded PLLatinum PLLs
• LMK01000 Family - < 30 fs High Performance Clock Buffer, Divider, and Distributor for Clocks up to 1.6 GHz
• LMK03000 Family - Clock Jitter Cleaners with Integrated VCO
• LMK02000 Family - Clock Jitter Cleaners for use with external VCXO
• LMX2531
  Frequency Synthesizer System, Integrated VCO

The Signal-Path Designer® is published every other month, the Signal-Path Designer newsletter's feature articles cover signal-path design techniques:

• Signal-Path Designer #116
  Energy Efficiency and Reliability in Automatic Transmission Systems
• Signal-Path Designer #115
  Liquid-Level Monitoring Using a Pressure Sensor
• Signal-Path Designer #114
  Continuous-Time Sigma-Delta A/D Converters.
• Signal-Path Designer #113
  A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video.

• AN-1558 - Clocking High-Speed A/D Converters
• AN-1704 - High-Speed ADC Input Driver
• AN-1716 - Driving High-Speed ADCs
• AN-1718 - Diff Amp Apps Up to 400 MHz
• AN-1719 - Noise Analysis - Fully Diff. Amp
• AN-1721 - High-Speed ADCs - Interfacing, Driving, and Clocking
• AN-1727 - Calibrating the ADC083000 Family of Ultra High-Speed Converters

The reference designs include ADCs, front-end amplifiers, timing components, and power supply regulation.

• ADC16DV160 - High-IF Sub-Sampling Receiver System
• ADC16V130 - Low Intermediate Frequency Receiver System
• ADC083000 - Lowest Power 8-bit 3 GSPS Data Acquisition System
• ADC14DS105 - Low Intermediate Frequency Receiver System
• ADC14V155 - High Intermediate Frequency Receiver System

WaveVision Data Acquisition and Analysis System
Test and evaluate A/D converters with National's easy-to-use WaveVision software, which supports National's latest ADC evaluation boards.

Challenges of clocking a high-definition world – Part I: foundational concepts
Clocks and jitter affect all aspects of system performance, including signal-to-noise ratio (SNR) and throughput; understanding and implementing today's ever-higher-speed clocks is crucial.

Challenges of clocking a high-definition world – Part II: A system applications perspective
Part II examines issues specific to communication systems that are evolving from multi-module, single channel architectures to single-module architectures. The article also shows how to analyze the impact of multiple, uncorrelated noise sources on overall SNR, relate this to clock jitter, and present an example that illustrates the different jitter requirements for different ADC resolutions.

Use in-the-loop gain control to extend dynamic range.
Modern communications systems are demanding more dynamic range than current analog-to-digital converters (ADCs) can support. One way to gain system dynamic range is to use a digitally-controlled variable gain amplifier (DVGA) with a high-speed, high-resolution ADC in a digitally-controlled AGC loop.