A Profile of a Quality Network Department
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RTS staff load test boards with National ICs.
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Pity the integrated circuit (IC) that falls into the hands of the Reliability Test Services (RTS) Lab.
Located in Santa Clara building D, the lab can be best described as an IC boot camp. "The environmental systems are running 24 hours a day, seven days a week," says Frank, lab manager.
Any chip that passes muster in this lab bears the National World Mark. National will not sell its new designs until they've been sampled in the Reliability Test Lab – a 168-hour test taking up to three weeks for most products (new packages and processes can require up to six weeks or 1000 hours testing).
National tests all new products, processes, packages, revisions, and design changes by sampling, usually about 77 ICs. Throughout the testing, engineers can track the samples' progress online.
Here's how parts are tested: A Reliability Engineer initiates the testing process by submitting a request to the lab with an approved Qualification plan. The planner then initiates a lot traveler with the information pulled from a Qual plan and sets up the proper paperwork for each stress test. The Product Engineer can submit a request directly to RTS for engineering runs or "look ahead" lots.
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RTS staff member enters test board tracking numbers into a database that can be accessed by engineers around the company.
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The board will be built with a representative collection of passive components around the test chip to simulate a real-world product. A burn-in board designer mocks up a sample test board based on the product line's specifications and submits it to the product line for approval.
New boards are tested as they come in, and again when they're used for future tests.
The lab electrically tests the new chips prior to their environmental stress test. "We want to be sure we're starting with working parts," says the RTS Lab Manager. "Occasionally we'll have to call in an engineer when we find a part that isn't working."
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RTS Lab Manager checks an Adec station.
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The test chips are hand-mounted on test boards. The boards are scanned for tracking and then taken to a cavernous room where they're placed in huge burn-in systems for environmental tests – heat, cold, humidity, and pressure.
Preconditioning
Based on the package sensitivity and their board mount techniques, different preconditioning stress tests have been defined for different package types. The preconditioning tests simulate stresses experienced by the parts during transit to the customer and board assembly.
After preconditoning, four tests are conducted:
Temperature Humidity Bias (THBT)
- 1000 Hr @ 85°C/ 85%RH, Static
- Read @ 48, 168, 500, 1000 Hrs
Autoclave Temperature and Pressure (ACLV)
- 96 Hr @ 121°C/100% RH, Unbiased
- 15 PSIG, Read @ 168 Hrs
Temperature Cycle (TMCL)
- 1000 Cycles @ -65°C/150°C, or –40c to 125c Unbiased
- Read @ 200, 500, 1000 Cycles
Operating Life Test (OPL)
- 125°C @ 168, 500, 1000 Hrs
These tests confirm the reliability of the mold compound, packaging, lead frames, and the circuit itself.
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THBT (temperature, humidity bias test) chambers put the ICs through temperature and humidity stress tests.
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These ADEC systems conduct various environmental burn-in tests.
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RTS staff inspect all burn-in boards before every test for functional integrity.
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When tests are completed, the chips are turned over to CTMG Test Services for a final round of electrical tests.
Environmental demands placed upon ICs keep increasing. Today's ICs are indispensable for products used in demanding environments, like car engine compartments, in satellites, and in military vehicles.
The Reliability Test Services Lab's test results help reassure our customers that National products will work under the most demanding conditions without fail.
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