Metrics: Reliability

Available Reports

PPM/FITS Summary: A graphical trend of National Semiconductor's Reliability Performance.

PPM/FITS - By Process: Failure Rates of Major Processes at National Semiconductor.

Package Data: Failure Rates of all Packages at National Semiconductor.

In reviewing this data, it may be helpful to refer to our Process by NSID Cross Reference Table (pdf: 1.8MB) and information on our Reliability Testing Programs.

Purpose of this Metric

• To provide a periodic monitor of product reliability under accelerated test conditions on wafer fabrication and assembly processes.
• To provide fab process and package reliability performance characteristics to customer.

Audit Strategy

• Package/Assembly processes are audited by Autoclave (ACLV), Temperature and Humidity Bias Test (THBT) and Temperature Cycling (TMCL) tests.
• Wafer fabrication processes are monitored by EFR and Long Term High Temperature Operating Life (OPL) tests.
• Devices are selected within each package and process audit groups based on representability and high manufacturing volume. Each audit group contains at least 3 devices.

Test Frequency

PPM/FITS Summary 

National Semiconductor conducts a Long Term Audit (LTA) program in order to identify trends in reliability of our products. The chart below displays the Early Failure Rate (PPM) and Long Term Life Failure Rate (FITS) trends for these products.

The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

The trend lines for both PPM and FIT rates illustrate the positive year to year reliability improvements at National Semiconductor.

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PPM/FITS by Process 

The following table lists Early Failure Rates in parts per million (PPM ) and Long Term Failure Rates in units per billion device hours (FITS) for the wafer fabrication processes.

The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

The data used to calculate the failure rates was obtained from OPL tests performed in the Reliability Monitoring Program.

These failure rates are updated quarterly with data through the end of the preceding quarter.

Period Covered: 29th Feb 2004 to 23rd Nov 2008

Last Updated: 12th March 2009

Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
.35	0	18700	0	0	1290000	3	366041022
.5	0	13425	0	0	932500	4	264599421
ABCD150	0	31520	0	0	3739000	1	1060951459
ABIC	0	15413	0	0	2558000	2	725839484
BICMOS8	2	12313	163	0	1407500	3	399381968
BIFET	0	12335	0	0	975000	4	276658912
CBIC	0	8370	0	0	1335000	3	378809895
CMOS	0	18680	0	0	2425000	2	688100371
CMOS7	0	16561	0	0	954000	4	270700104
CMOS8	1	12195	83	0	1410500	3	400233226
CMOS8T	0	16395	0	0	1780000	2	505079860
CMOS9	1	6382	157	0	923000	4	261903770
CS065	2	34108	59	0	3862000	1	1095853045
CS080	0	29095	0	0	2720500	2	771949303
CS100	1	13986	72	0	898000	4	254809951
CS150	1	13275	76	0	932500	4	264599421
CS200*	0	9850	0	0	3375000	2	957665465
DLM	0	9080	0	0	1585000	3	449748077
HV700	0	13580	0	0	1222500	3	346887713
LB250	0	18835	0	0	1705000	3	483798405
LB300	0	32249	0	0	3406500	2	966603676
LFAST1	0	18610	0	0	2335000	2	662562625
LMDMOS	0	16810	0	0	2200000	2	624256007
LS JI SLM*	0	800	0	0	100000	36	28375273
P2CMOS	0	48295	0	1	4172500	2	536440139
PVIP050	0	9600	0	0	765000	5	217070838
RFCMOS	0	2055	0	0	370000	10	104988510
SLM	0	42786	0	0	3352500	2	951281028
TS060D	0	8860	0	0	612500	6	173798547
TS100	0	8190	0	0	900000	4	255377457
VIP 10	0	11856	0	0	1065000	4	302196657
VIP III	0	14765	0	0	12125000	3	344050185
VIP III H/HU2	0	2366	0	0	702554	6	199351615
VIP1+	0	21850	0	0	2515000	2	713638117

Note: PPM is a point estimate based on rejects and sample size for EFR.
* - Data from previous time range 02/24/2003 - 02/27/2004

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Package Data - Reliability Monitor Plan 

The following tables list failure rate in percentage (PCT) for packages. The data used to calculate the failure percentage was obtained from ACLV, THBT and TMCL tests.

These tables are updated quarterly with data through the end of the preceding quarter.

Percentage = Rejects/Sample size * 100
Period Covered: 29th Feb 2004 to 24th Feb 2008
Last Updated: 27 August 2008

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