Failure Analysis

National Semiconductor's long established Failure Analysis group provides on-going support for quality efforts with state-of-the-art equipment and best-of-class services.

What is "failure analysis"?

Typically, when in-depth investigations are desired on a suspected failed device, instructions for disposition of the failure are often, "Go do FA" or "Give the part to FA". Moreover, the process of "failure analysis" (FA) occurs at all levels and within all business processes of any large business organization. Even within the context of the quality and reliability of integrated circuits ("ICs"), a number of definitions may come to mind, e.g., FA - the organizational group, FA - the work process, or FA - the engineering discipline. These terms and meanings are utilized interchangeably in the semiconductor industry. Because of the multiplicity in definitions, there exists the possibility for misunderstanding and misinterpretation.

At National Semiconductor, no group is expected to be self-contained and possess the complete expertise to address all possible concerns, and so a team-centered and interdisciplinary approach is practiced. The Product Quality Assurance ('PQA') work process makes full use of this and is designed to resolve concerns regarding the nature of defects detected on devices returned to NSC. Assistance from other engineering and manufacturing groups is frequently utilized by WQN to address PQA concerns. The various WQN sites around the world operate autonomously, but in partnership to share information and resources.

Although any individual or team may perform FA (the work process), Failure Analysis groups exist within WQN to help support the failure analysis activities; typically, those that may require exhaustive die-level analysis. This focus of the rest of this article will be on the work processes particular to WQN and the FA Groups in WQN.

Typical FA Flow

The FA workflow is embedded within the PQA process and typically includes the following broad steps:

• Assure failure validity
• Fault localization and characterization
• Sample preparation and defect tracing
• Root cause determination

Assure failure validity

All customer-generated documentation is retained for review by the analyst. A clear and detailed description of the device history and usage, characteristics of the failure, and any analytical findings prior to the device being returned to NSC will aid the investigation and timely resolution of the PQA submission. Historical databases that exist within WQN are reviewed to provide additional perspective and guidance. After a review of this information, an initial analysis strategy is formed. It should be noted that not all devices, even within the same request, will be analyzed in exactly the same manner. Different analytical approaches may be necessary to reach a better understanding of any failure mechanism. Confirmation of the reported failure mode should occur prior to further analysis steps. Good correlation to reported failure modes insures confidence in any subsequent findings. Bench-top test ('bench test') equipment, such as curve tracers or application-based bench testing, and production-level automatic test equipment ('ATE') may be used for electrical characterization.

Fault localization and characterization

Following normal correlation steps, the failure is electrically characterized to aid the localization of any physical defect or perhaps more specifically, "Which circuit node (on the die) is failing?" In addition to further use of bench test and ATE, additional tools and techniques that may be utilized include:

• Software tools, e.g., layout and schematic databases
• Decapsulation (wet chemical or plasma)
• Imaging and probing techniques, e.g., thermal, optical, infrared, X-ray, acoustic, mechanical, and electron-beam
• "Microsurgery", e.g., laser, ion-beam

Sample preparation and defect tracing

The next question to be solved by the failure analyst is, "What circuit element is causing the node to fail?" The transition into this step is not always distinct from the previous step, Fault Isolation and Characterization, and may be considered as a continuation of that process. For discussion purposes, the two steps are delineated in this article. In practice, iterations between the two steps are often required due to the layered construction of modern ICs, i.e., failure mechanisms are often 'buried' under overlying stratum. Tools and techniques utilized in this portion of the analysis include:

• Wet and 'dry' chemical, e.g., decapsulation, deprocessing, or 'delayering'
• Physical, e.g., polishing, cross-sectioning
• Focused Ion Beam (FIB) or 'Ion Mill' for cross-sectioning, creation of probe points, or 'circuit editing'
• Mechanical probing, e.g., for transistor characterization

Physical and chemical characterization of fault

The physical cause of device failure, once localized and identified, may require further characterization to aid in determination of the source or generating set of circumstances of the mechanism, i.e., a root cause. On one hand, the mechanism may be recognized by physical features alone, e.g., optically identified, or may require more characterization by materials analysis techniques. Examples of these are energy dispersive spectroscopy (EDS) and transmission electron microscope (TEM), and are discussed in another article. Typically, a failure analyst would submit requests to resources available within WQN to accomplish this work.

Root cause determination

Some controversy may revolve around Root Cause determination; however, under most circumstances the usual workflow (which is the most efficient and expedient process) is that the failure analyst transfers responsibility to other WQN engineers to pursue with an appropriate group, e.g., Design, Process, Assembly, or Test, depending on failure analysis findings. An atmosphere of a 'learning organization' is fostered, utilizing 'lessons learned' databases and a 'best practices' sharing can occur with the full support of embedded quality systems and management reviews.

Summary

Failure Analysis is a critical step in the process that strives to discover physical evidence that clearly identifies the cause of failure. This evidence is sought through the analysis on a case-by-case basis of failed integrated circuits. Electrical and physical analysis is performed using an array of straightforward and sophisticated analytical measurement systems, bench top equipment, and techniques. Using the appropriate equipment and work processes, the location of the cause of failure is isolated on the die and physically characterized.

Collaboration with other engineering disciplines, e.g., product, test, design, assembly and process, is utilized to move analyses forward. Analysis progress, results and conclusions are communicated to internal and external contacts supporting the Containment and Corrective Action processes to identify a process owners who can implement changes to limit and eliminate the cause of failure. Failure mechanisms typically identified include: electrical overstress (EOS), masking/etch anomalies, mechanical damage, emitter-base (EB) junction damage, capacitor oxide pinholes, electrostatic (ESD) damage, gate oxide ruptures, and test coverage issues.