System Test Access (SCAN) FAQs from National Semiconductor
System Test Access (SCANSTA) FAQs
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How does the SCANSTA111 work with a JTAG connection?
The STA111 (aka "SCAN bridge") is a device that enables the user to partition scan chains. Functionally it is analogous to an addressable switch for steering 1149.1 vectors to multiple cards or to numerous local loops of devices. This is particularly useful in systems that have multiple configurations, i.e. multiple boards that may be present or not - such as a backplane environment. The 'STA111 is also useful for partitioning scan chains within a board for applications where it is prudent to divide the test bus into functional blocks, or where multiple CPLD's are being accessed by IEEE 1149.1.
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Can the SCANSTA111 be placed on the backplane instead of directly on the boards (pros and cons of doing this)?
Yes it can, however we see nothing positive in doing this, yet on the negative side you'll be adding pins to the connector between boards and the backplane. The best approach is to place the STA111 on the board itself.
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Is the STA111 cascadable?
Yes. However, not all ATPG vendors support heirarchy of STA111 devices, please check with your preferred ATPG vendor.
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We're concerned with our application meeting the setup and hold times for the clocks as the circuitry to be tested is on several different cards. Is the SCANSTA111 data shifted out on the rising clock edge and is the data shifted in at the destination on that same clock edge?
Data is presented on TDOb & TDOn on the falling edge of TCKb, and captured on TDIb & TDIn on the rising edge of TCKb (following the rules in IEEE Std. 1149.1).
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Our design has some unique power modes, can you explain the state of the STA111 I/O during the various tristate modes so we can ensure we properly place pull-up or pull-down resistors on the necessary pins?
On the Backplane side: TRISTb follows the state of TDOb. When TDOb is TRI-STATE, TRISTb is high. When TDOb is driving, TRISTb is low. TDOb follows the rules set in IEEE Std. 1149.1 (TDOb only drives data during data shift operations and is TRI-STATE at all other times). TDIb, TMSb and TRSTb all have pull-ups per IEEE Std. 1149.1. TCKb does not have any pull-up.
On the LSP side: When TDOn is TRI-STATE, TRISTn is high. When TDOn is driving, TRISTn is low. When Local Scan Port n (LSPn) is active, TDOn follows the rules set in IEEE Std. 1149.1 for the TDO pin (TDOn only drives data during data shift operations and is TRI-STATE at all other times). The only situation where TCKn, TMSn, TRSTn and TCKn are TRI-STATE, is when the OE pin is driven high. At all other times they drive a high or low. There are no pull-ups on outputs. TDIn does have an internal pull-up.
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Don't I need a BSDL file for the STA111 device?
The STA111 BSDL file is on National's web page. The device supports the extest instruction, but only on a limited number of pins.
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Is the SCANSTA101 needed in the system or could the boundary scan be completely controlled from the outside? How could this be implemented?
The delivery of 1149.1 vectors can come from an external source such as those provided by the third party ATPG vendors, or you can embed the vector delivery into the system using the 'STA101. The strategy you use for the architecture of your particular design would have to be developed based on your end system goals. Initially, at the board level, you probably want to be able to test each board independently using 1149.1. You just need a method to talk to the 1149.1 bus on the board to deliver the test vectors you developed with the ATPG tool. Once the board is in the system - in a backplane with other boards - if you provide a backplane 1149.1 bus, and place a STA111 on each board, you can still test the system using the ATPG tools and hardware for vector delivery providing you can physically get to the 1149.1 connector pins. If you would like to embed this entire test capability into the system, then you need a controller, a master device (STA101), and a place to store the vectors.
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Why is there memory in the STA101?
The STA101 has been optimized for fast vector delivery in applications such as delivering programming or configuration vectors using the 1149.1 bus. Consider interfacing a 16-bit parallel bus operating at 66Mhz to a serial 1149.1 test bus operating at 25Mhz. If the processor is dedicated to this task, then there is a large amount of wait time while the vectors are delivered. In an advanced system, multiple STA101's could be used to deliver large amounts of data to multiple 1149.1 scan chains. The memory can be loaded with the vectors, and the processor could manage multiple STA101's to obtain the highest vector throughput.
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If the boundary scan code were to be stored in the unit, is additional memory required or can the code be stored in SCANSTA101 IC?
Additional memory will most likely be required as the memory on the STA101 is only about 2KB. The STA101 memory is only provided as a cache to speed up the vector delivery process by freeing up the processor.
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Does the SCANSTA101 need to be located on a board containing a processor or can it be placed on a different board and run communication lines to the processor?
It can be placed on a different board, but, the STA101 requires Address, Data and control lines. This may be too many signals to route across the backplane. It is possible to put the STA101 on the other side of a bus adapter, such as a PCI bus adapter.
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If the system does not have a processor onboard (all processing being handled by a different unit, generating all the information.) How could boundary scan be handled using the SCANSTA101 & SCANSTA111)?
Although the SCANSTA101 and the SCANSTA111 both support the IEEE 1149.1 test bus infrastructure, they both perform two unique functions. The STA101 is used for vector delivery. Vector deliver can be embedded internally on the system, or it can be from an external source such as the hardware and/or software provided by our third party ATPG partners. The STA111 is used for scan path management. With the STA111 you can create a multidrop environment for use with multiple boards, and you can partition scan chains into smaller, more manageable local scan chains. The STA101 and STA111 do not have to be used together, although they can be.
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How many SCANSTA111's can you drive with a SCANSTA101?
From a DC perspective the STA111 has a standard CMOS input structure which is a very high impedence. The DC leakage is typically in the order of 10's of uA. The STA101 *_SM outputs are all rated to drive 24mA at voltage values that correspond to "1" and "0". Even 30 STA111 inputs at "10's of uA" will not overload the output capability of the STA101 *_sm outputs in the DC case.
For the AC case, CMOS inputs are typically modeled as capacitors. Backplanes are modeled as transmission lines and then the system will run at a given frequency. All of this information needs to be taken into account before a design can be finalized.
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What is the SCANEASE Software?
SCANEASE, created by National Semiconductor, is a command line utility that is used to convert (ascii) SVF files (from any ATPG software) into an embedded vector format we call EVF2. The EVF2 is a binary embedded vector format, and it incorporates 1149.1 and the STA101 features into the EVF2 file. Drivers for the STA101 read the EVF2 while the I/O drivers deliver the vectors in an embedded environment. Wrappers for a particular embedded environment are provided by the user (i.e.; PCI, PCMCIA, 1553, etc).
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How much does SCANEASE cost?
It's free with the use of the SCANSTA101. The EVF2 that is generated cannot be used with any other device as the functionality and features of the STA101 are imbedded into the binary file.
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Can I use SCANEASE even if I don't use National Products?
SCANEASE has no utility except when the STA101 is used. The format of the output vectors includes STA101 functional knowledge which cannot be understood by any other device.
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One of the big issues is BIST, from what I understand the boundary scan can be used as a start up BIST. Are there any possibilities that this system could handle run-time BIST?
The RUNBIST instruction is much like any other 1149.1 instruction. Therefore, the STA101 is fully capable to drive all 1149.1 vectors (this includes IEEE1532, Various FPGA formats, and FLASH patterns). From the STA111's perspective, it is able to syncronize the initialization of BIST regardless of the number of scan chains in a system.
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Do you have any reference designs or Demonstration Kits?
We do have an Evaluation Kit for sale. The kit includes a backplane with three daughtercard slots, and cards for evaluating the STA111 and the SCAN921023/1224 LVDS SerDes. For More information, go to our Evaluation Kit page.
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