Video Timing Solutions

National Semiconductor's High-Performance Video Clock Module
Provides Ultra Clean Clocks to Xilinx Virtex-5 LXT Development Kit to Deliver SDI-Conforming Jitter Performance

National's ML571-1982CLK clock module 

National's plugs into a Xilinx Virtex-5 development platform to create a complete video timing reference design for triple-rate (3G/HD/SD) SDI applications. This includes FPGA firmware (Verilog, VHDL source).

LMH1981: Multi-Format Video Sync Separator

• 50% sync slicing for superior HSync output jitter
• Horizontal sync output propagation delay <50 ns
• Bi-level & tri-level sync compatible
• Accepts video signals from 0.5 VP-P to 2.0 VP-P
• No external programming required
• 3.3V or 5V single supply operation

LMH1982: Multi-Rate Video Clock Generator

• 148.5 MHz output clock jitter as low as 40 psp-p (typ)
• Two simultaneous LVDS output clocks with selectable frequencies and tristate capability
  • SD clock: 27 MHz or 67.5 MHz
  • HD clock: 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz or 148.5/1.001 MHz
• Low-jitter output clocks may be directly connected to an FPGA SDI serializer to meet SMPTE jitter specifications
• Two reference ports (A and B) with H and V sync inputs
• Supports NTSC/525i, PAL/625i, 525p, 625p, 720p, 1080i, 1080p video timing
• Output Top of Frame pulse with programmable timing reduces required FPGA resources
• Supports cross-locking, allowing the outputs to be locked to a reference with a different timing format
• External loop filter allows control of PLL loop bandwidth, lock time, and input sync jitter rejection
• Free run or holdover operation on loss of reference
• User defined free run control via VC_FREERUN input
• I2C bus interface for programming device registers and reading device status
• 3.3V and 2.5V supplies

National Semiconductor Enables the Xilinx Virtex 5 FPGA
to Comply with SMPTE Jitter Requirements

The ML571-1982 CLK reference clock module features National Semiconductor's highly-integrated multi-rate video clock generator. The LMH1982 can generate two simultaneous SD and HD output clocks genlocked to either the recovered H and V syncs from a Xilinx Virtex-5 LXT FPGA or from the outputs of an LMH1981 sync separator. Additionally, the LMH1982 provides an output Top of Frame timing pulse. In the event of a loss of reference, the device can be configured to default to either free run or holdover operation.

This reference design provides a proven video clocking solution for FPGAs that complies with stringent SDI jitter requirements, including the stringent SMPTE 424M standard for 3G-SDI. Integration, ease and flexibility of design, are demonstrated by the LMH1982 requiring a few additional components, and only one 27 MHz VCXO. An additional benefit of the LMH1982 is the programmable charge pump current control register for dynamic control of PLL bandwidth. A wide loop bandwidth can be programmed for faster PLL lock time or a narrow loop bandwidth can be programmed for maximum input attenuation.

The LMH1981 and LMH1982 provide a high-performance clocking solution that requires minimal PCB area, as shown in the photo below, contrasting with the multiple discrete XO-based PLL clocking.

FPGA IP, available from National, demonstrates the flexibility, functionality and performance of the LMH1981 and LMH1982. National provides source and executable binaries, together with associated documentation, to enable a comprehensive evaluation of National’s video timing solution with Xilinx’s Virtex-5 LXT Serializer and Deserializer (SerDes).

The FPGA firmware includes:

• Triple-rate (3G/HD/SD) SDI serializer demo with internal test pattern generation
• Triple-rate SDI SerDes reclocking/pass-through demo with automatic rate detect
• Genlock support for analog reference or SDI inputs
• Support for all popular SD, HD, and 3G “type A” video formats
• I²C control interface

Video Timing Resources:

See all of National's SDI/Broadcast Video Solutions including SerDes, cable drivers, equalizers, and reclockers.

• Video timing products parametric table
• LMH1981 Datasheet - Multi-Format Video Sync Separator
• LMH1982 Datasheet - Multi-Rate Video Clock Generator with Genlock
• LMH1982 Product Brief (pdf 822KB)
• Signal Path Designer #106, Timing is Everything - The Broadcast Video Signal Path
• Signal Path Designer #113, A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video
• Analog Edge, July 2006 article, Improving Video Clock Generation in Modern Broadcast Video Systems
• Broadcast Video Owner’s Manual / LVDS Owner’s Manual
• Broadcast Video Selection Guide (pdf download page)

SDI Evaluation Boards:

• SDALTEVK - Triple-rate SDI & video clocking daughter card for Altera Cyclone III FPGAs
• SDXILEVK - Triple-rate SDI & video clocking daughter card for Xilinx Spartan-3A/3E FPGAs

Ordering Info

• National ML571-1982CLK Evaluation Board
  

Related Featured Sites:

• SDI/Broadcast Video Solutions including SerDes, cable drivers, equalizers, and reclockers
• Other clock and timing solutions including jitter cleaners, clock distribution, level translators, and PLLs
• Products for analog RGB video
• Displays Products
• Interface Solutions