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System Test Access IEEE 1149 (JTAG) Solutions


SCANSTA products provide support for a system or card-level IEEE 1149.1 (JTAG) bus architecture. The JTAG mux is used for multiplexing and managing multiple JTAG chains, while the embedded master simplifies connecting the JTAG bus to a microprocessor bus.

Featured Product: SCANSTA476 - Analog Voltage Monitor - The SCANSTA476 is a low-power, 8 channel analog voltage monitor.  It is useful for manufacturing or online testing.  The JTAG interface is used to select the input, initiate measurement, and access the results.

Featured Article: JTAG Advance Capabilities and System Design
Signal Path Designer #117 (pdf) - Overview, Applications, Configurations, and JTAG uses.

 

NEW Design Tools:

Common Uses of JTAG:

 




SCANSTA Product Selection Table

Order Number Function No. of Ports Package
SCANSTA476 Analog Voltage Monitor 8-channel LLP-16
SCANSTA112 Multiplexer 7-port FBGA-100 and TQFP-100
SCANSTA111 Multiplexer 3-port FBGA-49 and TSSOP-48
SCANSTA101 Master   FBGA-49

 

Select

Selection Table (Catalog view):

Featured SCANSTA Products

Selection Guides:

BIST w/JTAG
The SCAN921023/1224 SerDes chipset features on chip BIST capability accessible via the JTAG port!

SCAN921023 / SCAN921224


 

Design

SCANSTA101 DESIGN GUIDE - Coming Soon!

Quick Reference Cards: Quick reference for SCAN STA device registers and operation.

Featured Application Notes and Technical Documentation:

  • AN-1259 - SCANSTA112 Designers Reference

SCAN Application Note Table: 

SCAN Technical Document Archive -
White Papers, Articles, Conference Papers and other JTAG information.

Evaluation Kit Information:

Frequently Asked Questions

Software & Models

Software Tools:

  • NEW - EVF Workbench - Graphical User Interface tool for conversion of SVF files to National Semiconductor’s EVF2 embedded file format.  Zip file includes readme file, license file, and setup program (1.6MB)
  • SCANEASE - SCAN Embedded Applications Software Enabler for the SCANSTA101 – source code and libraries for EVF2 embedded file format delivery.  Zip file includes source code, libraries, and examples. (2.5MB)

Models:

 

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Useful Links

DfT/BIST Insertion

ATPG

CPLD/FPGA

Loaner SCAN Backplane EVAL System