LVDS and SerDes Design Guides -- National Semiconductor
| Design Guide |
LVDS Design Guide Description |
LVDS Owner's Manual
(4th Ed) |
This design guide compiles the information and concepts that you will need to save you valuable time and money and maximize the benefit of using National's Low-Voltage Differential Signaling (LVDS) solutions. This third edition of the LVDS Owner’s Manual is an easy-to-read compendium that contains useful information for everyone. There is an introduction to the technology, concepts, and applications for someone just starting to design with LVDS. We offer guidance on how to select the right LVDS device and family for your application whether it is chip-to- chip, mezzanine-to-mezzanine, or box-to-box. Perhaps most helpful is our guidance for proper selection of cables, termination, and backplane design considerations. |
16-bit SerDes Design Guide
(pdf 3MB) |
Product featured: DS92LV16
The DS92LV16 is a member of National’s robust and easy-to-use Bus LVDS serializer/deserializer (SerDes) family already popular in a wide variety of telecom, datacom, industrial, and commercial backplane/cable interconnect applications. The DS92LV16 is similar to the original 10-bit Bus LVDS SerDes products, but provides a wider, 16-bit data bus payload.
The DS92LV16 is very flexible and performs over a wide, 25 - 80 MHz frequency range. Both the transmit clock and receiver reference clock have high jitter tolerance, allowing the use of low cost clock sources. |
18-bit SerDes Design Guide
(pdf 3MB) |
Products featured: DS92LV18, SCAN921821
The DS92LV18 and SCAN921821 are members of National’s robust and easy-to-use Bus LVDS serializer/deserializer (SerDes) family already popular in a wide variety of telecom, datacom, industrial, and commercial backplane/cable interconnect applications. They are similar to the original 10- and 16- bit Bus LVDS SerDes products, but provide a wider, 18-bit data bus payload to support not only byte-oriented data but also carry other information such as parity, frame, control, status, sync, low frequency bus or clock signals, etc.
The DS92LV18 and SCAN921821 are very flexible and performs over a wide, 15 - 66 MHz frequency range. Both the transmit clock and receiver reference clock have high jitter tolerance, allowing the use of low cost clock sources. |
Channel Link Design Guide
(pdf 3.4 MB) |
Products featured: DS90CR21x/28x/48x, 21/28/48-bit Channel Link SerDes
National Semiconductor’s DS90CR2xx and DS90CR4xx Channel Link serializers/deserializers (SerDes) are among the easiest to use SerDes in the market. Unlike most SerDes, Channel Link serialize wide buses, require no synchronization training characters or patterns, require no clock source at the receiver end. Channel Link SerDes have the lowest cost per gigabit and are among the lowest power SerDes chipsets in the industry. |
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