SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint with IEEE 1149.6
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint with IEEE 1149.6
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2x2 LVDS 1.5Gbps Crosspoint Switch with Pre-emphasis and IEEE 1149.6
The SCAN90CP02 is a low power, 1.5 Gbps 2 x 2 LVDS switch with programmable pre-emphasis and IEEE 1149.1 (JTAG) & 1149.6 testability. Its non-blocking architecture and very low jitter make it ideal as a switch, buffer/repeater, 1:2 splitter, or 2:1 mux in high speed switching and redundancy applications.
Pin-programmable pre-emphasis dramatically reduces jitter caused by lossy backplane and cable interconnects, boosting the signal quality and extending the reach of existing LVDS signals from SerDes, FPGAs, or ASICs. It's a physical property of backplanes and cables that they attenuate higher frequencies more than lower frequencies. Since the 1.5 Gbps signal is composed of a spectrum of frequencies, the interconnect attenuates the high frequencies more than low frequencies, which distorts the signal and makes it harder for the receiver at the far end to properly interpret the signal without errors.
Pre-emphasis “pre-distorts” the original signal to give it more high frequency content. Programmability allows the designer to tune the pre-emphasis level to approximately cancel out the high frequency loss caused by the cable/backplane.
Testability features include IEEE 1149.1 (JTAG) and 1149.6 to test TTL and LVDS connections between the pins and other devices on the board, plus supplementary JTAG-initiated fault insertion to verify system redundancy and failsafe modes work properly.
We also have an Evaluation Kit available, the SCAN90CP02EVK.
Other Important Links:
IEEE 1149.1
The SCAN90CP02 supports a fully compliant IEEE 1149.1 interface. The Test Access Port (TAP) provides access to boundary scan cells at each LVTTL I/O on the device for interconnect testing. The TAP also provides access to the IEEE 1149.6 test features if AC-coupled interconnects are used, and access to the fault insertion features
For more information about IEEE 1149.1, refer to the IEEE website or the SCAN90CP02 BSDL file.
IEEE 1149.6
AC-coupled differential interconnections on very high speed (1+ Gbps) data paths are not testable using traditional IEEE 1149.1 techniques. The IEEE 1149.1 structures and methods are intended to test static (DC-coupled), single ended networks. It is unable to test dynamic (AC-coupled) digital networks because the AC-coupling blocks static signals. The SCAN90CP02 - which is intended for use in up to 1.5 Gbps data paths - has been designed with IEEE 1149.6 support to enable test of AC-coupled interconnects.
For more information about the IEEE 1149.6 standard, refer to the IEEE website or the AC-Extest Working group site.
Fault Insertion
High availability and faul tolerant systems are typically designed with mechanisms to evaluate various fault conditions. The most common condition, referred to as "StuckAt" faults, occur when a bit is stuck high, or stuck low. These faults can be simulated using the SCAN90CP02 by initiating the fault insertion features. Using the IEEE 1149.1 port, a fault can be inserted into the data path using a special JTAG instruction and register for the StuckAt feature.
For more information on the SCAN90CP02 DfT Features, refer to Applications Note AN-1313
We also have an Evaluation Kit available, the SCAN90CP02EVK.
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