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Designers of portable electronics and small form factor applications are challenged by the need to increase functionality while decreasing the layout size. Some solutions are incorporating system-on-a-chip designs to improve integration but often this approach can not keep pace with the timing of market demands or the application cost requirements. Converting surface mount package designs to either chip-on-board (COB) or flip chip can result in a 75% to 90% footprint layout reduction utilizing the same functional device design.
Since package outlines are standardized and the die sizes used in these packages vary from device to device, each die-package combination has a different die size to package size ratio. In addition each package has unique interconnect layout requirements. By utilizing unpackaged die in a design layout the silicon to interconnect ratio can be reduced significantly resulting in more efficent use of board/substrate area. Both COB and flip chip implementations provide a high silicon to substrate ratio as compared to the alternative packaged silicon approaches.
National Semiconductor’s die products are available for implementation in wirebond COB chip applications. This format will provide designers with an option to improve integration and decrease layout area.
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