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Flip Chip
Flip chip assembly offers optimized electrical performance in addition to optimized miniaturization. Die in flip chip format also demonstrates extremely high assembly yields, resulting mostly from the self alignment properties of the reflow process. However, the opportunity to control signal integrity from the die through the substrate to other die on the substrate or even packaged die on the substrate may provide the most significant benefit of flip chip assemblies.
The variety of substrates available for Flip Chip applications allows a wide selection of electrical, thermal, CTE and mechanical properties tailored to specific application requirements. Ceramics and glass ceramics offer stable dielectric constant, low dielectric loss tangent and good thermal dissipation. Organic substrates can provide low dielectric constant and light weight as well as, in many cases, low cost.
The Flip Chip assembly process flow consists of four essential steps; die bumping, die attach, interconnect and underfill. Bumping is generally provided by either the die supplier or a contract bumping house. Die attach and interconnect provides the mechanical and electrical connection of the die to the substrate and wiring pattern on the substrate simultaneously. The surface tension of molten solder wetting the pad on the substrate provides self alignment between the bumps on the die and the land pads on the substrate. The die placement must ensure at least 30 – 50 % overlap of the appropriate substrate pad by the correct bump on the die. Flip Chip bonding requires a flux application to pads on the substrate in order to ensure strong bonds as well as high production yields. Particular process characteristics and considerations for Flip Chip assembly detailed below should prove helpful in understanding how to select and specify product applications.
Solder Flux
The variety of techniques for fluxing include dipping the solder bumps into the flux as well as
stencil printing, pin transfer and flood or spray coating of the substrate. Precision application (dip, stencil, pin transfer) are preferred to minimize residue and cleaning challenges.
Die Placement
Due to the self alignment characteristics of solder, a bump pitch of 200-225 microns only demands placement accuracy of + 75-125 microns and + 1 degree rotation. This compares to a placement accuracy requirement of + 40 microns for 0.4 mm pitch QFPs or + 50 microns for 0.5 mm pitch CSPs.
Reflow
Conduction or vapor phase reflow provides optimum process control and ultimate solder joint consistency and reliability. However, more commonly available infrared and convection reflow equipment leads to more widespread application of these techniques. As with surface mount reflow, even temperature distribution and controlled temperature ramping, both up and down are critical to yield and quality.
Flip chip eutectic solder bump reflow to substrate
Underfill
Underfill enhances thermal and mechanical vibration fatigue reliability as well as mechanical shock resistance of the flip chip solder joints. Most underfill application relies on capillary flow demanding well controlled materials properties including viscosity and adhesion as well as the cured state properties of thermal transfer, coefficient of thermal expansion and mechanical strength.
Encapsulation
Either liquid encapsulation or transfer molding may provide the physical protection for the die. For high volume applications as well as those which can be fit into standardized mold cavities, transfer molding provides the lower cost alternative. Transfer molding also ensures consistent surfaces for marking. Larger modules and die mounted to large, mixed technology substrates generally demand liquid encapsulation. Liquid encapsulants come in two types, silicone or epoxy based. Silicone systems offer excellent moisture resistance and high compliance, but remain difficult to mark and difficult to handle. Epoxy systems provide improved adhesion and marking relative to silicone as well as more consistent appearance and smaller "keep outs" or die spacing specifications.
Marking
Laser, ink jet, stencil or stamp marking techniques may be employed although laser and ink jet simplify serialization of parts. Key factors include permanence, visibility and contrast. For silicone based liquid encapsulants laser marking works best. With epoxy liquid encapsulants and mold compounds ink based marking with either ink jets or pin printing provide maximum clarity and contrast.
Key Process and Design Issues
In Flip Chip assembly various design, process and manufacturing issues play a key role in guaranteeing high yield, high reliability product. During implementation and processing many problems can be avoided by giving attention to some common pitfalls. This section describes some simplistic but important sources of manufacturing difficulties that can easily be avoided.
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Typical Flip Chip Attach Process Flow |
- Smaller bumps provide tighter pitch and routing density but provide less stress relief due to mechanical stress and CTE mismatch.
Solution: Utilize underfills that match the die standoff height and bump to bump spacing to maximize flow rate and coverage.
- During initial manufacture of the substrate assembly opens and shorts testing is difficult to manage with live die causing debug difficulties.
Solution: Utilize die daisychains to debug manufacturing process.
- All eutectic solder bumps are not the same. Variations may cause yield and reliability problems.
Solution: Work with the supplier to understand the UBM, materials and solder bump buildup.
- Substrates utilizing eutectic bumped die and other SMT devices require various thermal processing.
Solution: Understand and design a process flow that considers the thermal hierarchy of the total substrate solution to guarantee yields and reliability.
- All components used in an application typically do not have uniform placement tolerances or I/O density, therefore requirements may vary.
Solution: Understand variants and partition the system accordingly.
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Design Guidelines
Many design rules depend on the specific equipment and process capabilities utilized. The guidelines presented here represent what we feel are nominal capabilities industry wide. If these guidelines are violated be certain to work with your assembler and suppliers as early in the design phase as possible to avoid major manufacturing, cost and quality implications.
Keep Outs
2500 microns typical.
Escape Routing
Peripheral or peripheral array layouts simplify escape routing reducing internal redistribution and routing through vias or through holes on other layers in the substrate. The number of routing layers may increase significantly with area array layouts.
Bond Line
Generally controlled by bump height following reflow. 125-250 microns typical.
Pad Size/Geometry
Width/Length = 75-100 microns (typical)
Pad Finish
8-10 micro-inch Au for most applications
Electrical Properties(typical values)
R = 0.002 ohms
C = 0.001 pF
L = 0.2 nH
Substrates
Substrate selection, particularly for system in package applications, control a great many aspects of a successful Flip Chip design. These include thermal management options, electrical performance, mechanical integrity and long term reliability. The table below presents several important properties of various substrate alternatives, most of which demand consideration in the design phase and have important impacts on cost and manufacturability as well.
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