CompactRISC Roadmap

CRX- CompactRISC Extensible
The Next Generation CompactRISC Architecture

Overview
The CRX is the next generation CompactRISC™ architecture. This architecture extends the earlier CR16 family of products by providing full 32-bit processing and memory space, additional registers, ultra-fast context switching and architectural extensibility features.

Architectural Features:

• 3-Stage Pipeline (Fetch - Decode - Execute)
• Three Operating Modes (User / System / Supervisor)
• Von-Neumann Bus Architecture with separate Instruction and Data Bus Interfaces, compliant to AMBA™ 2.0
• Up to 9 Register Banks (1 Supervisor Bank, up to 8 User Banks)
• 8 x 16-bit Instruction Queue
• Branch Target Cache (16 Entries)
• Load/Store Unit (LSU)
• 16 x 16 bit Hardware Multiplier (16/32/64 bit Result)
• 32-bit Barrell Shifter
• Address Calculation Unit (ACU)
• Q-Format Arithmetic Support Unit (ASQ)
• Condition Check Unit (CCU)
• Population Count Unit (CNT01)
• Coprocessor Interface
• Nexus5001 compliant On-chip Debug/Trace

The CRX implements a 32-bit embedded RISC architecture
Instructions are fetched into an instruction queue via an industry-standard AMBA™ AHB interface. A branch target cache keeps a history of branch target addresses in order to speed-up code loops. The data path elements, such as ALU, hardware multiplier and barrel shifter can work on multiple banks of 16 x 32-bit registers. A load-store unit decouples data transfers via the data AHB and allows the CPU to continue program execution while the data is being transferred from/to memory (in case there are no data dependencies). The processing capabilities of the CRX can be extended by attaching up to 16 coprocessors to the CPU.

Powerful debug features are implemented by the CRX, such as support for up to 16 hardware breakpoints on code and/or data.

Currently CRX – CompactRISC Extensible is not available for licensing through the IPextreme Licensing Program