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1. What is CompactRISC?
CompactRISC is a family of embedded RISC CPU cores that are designed, used and licensed by National Semiconductor. These CPU cores share a common architecture.
2. What makes CompactRISC a RISC architecture?
CompactRISC has a simple instruction set, which yields fast instruction decoding and execution and high throughput of up to 1 clock cycle per instruction. In addition CompactRISC is a load-store architecture. This means that only the load/store and bit manipulation instructions can access memory while all other instructions can access only registers.
3. What kind of pipeline is used inside the CompactRISC? What is its typical throughput?
CompactRISC uses a 3 stage pipelines. The pipeline stages are:
- Instruction Fetch
- Instruction Decode
- Instruction Execute
With this pipeline CompactRISC can deliver peak performance of 1 clock per instruction (CPI). However typical CPI rates are above this value and depend on the type of application. An average value of 1.6 clocks per instruction can be expected.
4. Does it support floating-point?
CompactRISC has no hardware floating-point support. Floating point is only supported by means of software emulation.
5. What kind of multiplier and divider does CompactRISC support?
The CR16CPlus core features a 16 x 8 bit hardware multiplier. In conjunction with the ALU and barrel-shifter, the multiplier achieves a considerable acceleration over bit-wise multiplication, at a reasonable cost (signed 8 x 8 = 16 bit at 1 cycle, 16 x 16 = 32 bit at 3 cycles). Simple Multiply and Accumulate Instructions are supported in hardware (16 x 16 = 32 bit at 4 cycles).
CompactRISC does not have an integer divide instruction. Division and modulus operations are supported by means of software emulation.
6. How many registers does CompactRISC have?
The CR16CPlus CompactRISC core has 16 general-purpose registers (R0..R13, SP, RA). Each two of the 16-bit general purpose register can form one 32-bit register. There are several processor registers like Program Counter (PC) Program Status Register (PSR). 3 Dedicated 32-bit registers for Interrupt Stack Pointer (ISP), User Stack Pointer (USP) and Interrupt Base (INTBASE) are available.
7. Does CompactRISC support big-endian or little-endian byte order?
CompactRISC supports little-endian byte order. This means that inside a word or a double-word the least significant byte resides in the lowest address and the most significant byte resides in the highest address.
8. Does CompactRISC have a fixed instruction length?
No. Unlike most RISC architectures CompactRISC does not have a fixed instruction length. This helps CompactRISC deliver more compact code and reduce program memory consumption. All CompactRISC instruction have an even instruction length. Instructions can be of length 2, 4 or 6 bytes.
9. Is there a way to perform an atomic (non-interruptable) read-modify-write memory operation with CompactRISC?
The CR16CPlus core provides bit manipulation instructions which allow atomic (non interruptible) bit setting and bit clearing directly on memory.
10. What types of stack does CompactRISC support?
The CompactRISC architecture support three stacks: The program user and supervisor stacks, and the interrupt stack. For the two core operating modes (user/supervisor) dedicated stack pointers are provided. The two stack pointers are managed by software and its usage conventions are described as part of the CompactRISC calling convention. The interrupt stack is automatically used by the CompactRISC cores whenever an exception is processed, to push the contents of the PC and PSR registers.
11. What type of exceptions does CompactRISC support?
CompactRISC supports traps, maskable interrupts and non-maskable interrupts.
12. What's the difference between an exception, a trap and an interrupt?
Exception is a general term for an exceptional event that breaks the normal instruction flow. There are several types of exceptions. Traps are exceptions that are triggered by an action of the program. An trap example is an attempt of a program to execute an undefined instruction. Interrupts are asynchronous events triggered by sources which are external to the core, like a timer.
13. Does CompactRISC support vectored interrupts?
Yes. When an interrupt occurs a CompactRISC core checks for the interrupt vector number and then looks for an interrupt handler address in a vector table called interrupt dispatch table. Control is then transferred to the interrupt handler.
14. Are interrupts always enabled in CompactRISC?
No. After reset interrupts are disabled. They can be later enabled. By setting the I-bit and the E-bit of the Program Status Register (PSR) all maskable interrupts are enabled. If the I-bit is cleared only non-maskable interrupts are accepted.
15. Does CompactRISC allow nested interrupts?
Yes, however, nested interrupts should be explicitly enabled by each interrupt handler. When an interrupt occurs, CompactRISC automatically clears the I bit in the PSR, thereby disabling nested interrupts. The interrupt handler can re-enable interrupts by setting the I bit. If it does so, nested interrupts will be acknowledged by the core while the original interrupt is being handled and the respective nested interrupt handlers will interrupt the execution of the original interrupt handler.
16. Does CompactRISC allow non-aligned data access?
Yes. Alignment restrictions on data access do not exist in CompactRISC. However non-aligned data access will result in an extra bus transaction during the instruction execution and this will increase the execution time by one or more clock cycles.
17. Does CompactRISC support memory-mapped I/O?
Yes. I/O registers are mapped to the CompactRISC address space and can be accessed using the normal CompactRISC memory access instructions i.e., the load/store and and bit manipulation instructions.
18. What debugging support is available in CompactRISC?
The CR16CPlus core supports software breakpoints using the breakpoint (BPT) trap. In addition debug support is given via NEXUS 5001 compliant debug interface accessible through a JTAG interface. This provides access to the core registers and gives full debug support with single step and up to 16 hardware breakpoints on instruction, address or data matches. Also direct memory access to the attached system bus is possible.
19. Is there a way to switch a CompactRISC core to low-power mode?
Yes. The CompactRISC WAIT and EIWAIT instructions suspend instruction execution in the core and significantly reduce power consumption. Typically an application will first switch the whole system to power down mode using a power management module, before executing one of those instructions. After executing WAIT or EIWAIT only an interrupt can resume instruction execution by the core.
20. Are there any limitations on the address of the interrupt dispatch table, interrupt stack and program stack?
There are no restrictions on the location of the interrupt dispatch table within the address space. This applies also to the interrupt stack, program and user stack.
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