CompactRISC CR16CP Architecture

• Architecture
• Register Set
• Operating Modes
• Memory Organization
• Exception Handling

• Instruction Set
• Addressing Modes
• Sample System Architecture
• On-Chip Debug

Architecture 

CR16CPlus Block Diagram

The CR16CPlus implements a 16-bit embedded RISC architecture. Instructions fetches and data transfers are performed via an industry-standard AMBATM AHB interface. A load-store unit decouples data transfers via AHB and allows the CPU to continue program execution while the data is being transferred from/to memory (in case there are no data dependencies). Powerful debug features are implemented by the CR16CPlus, such as support for up to 16 hardware breakpoints on code and/or data.

Architecture Features

• 3-Stage Pipeline (Fetch - Decode - Execute)
• Variable Instruction Length (16, 32 or 48-bit Instruction Length)
• Two Operating Modes (User / Supervisor)
• Von-Neumann Bus Architecture, compliant to AMBATM 2.0
• Load/Store Unit (LSU)
• 16 x 8 bit Hardware Multiplier (16/32 bit Result)
• 32-bit Barrell Shifter
• Nexus5001 compliant On-chip Debug

Register Set 

The CR16CP implements a configurable set register banks, consisting of one Supervisor register bank and up to 8 User register banks. Each of these banks comprises 16 x 32-bit registers.

In addition, there are dedicated control and status registers, coprocessor management and cache configuration registers.

The special debug registers are only accessible via an on-chip debug mode.

Operating Modes 

The CR16CPlus can operate in any of the following operating modes:

Supervisor Mode

• Entered upon occurrence of any exception (trap or interrupt)
• Uses SP as Program Stack Pointer
• Intended to be used for the Execution of Kernel Routines of an Operating System (OS)
• After reset CR16CPlus starts in supervisor mode

User Mode

• Can only be entered via Jump User instruction
• Uses USP as Program Stack Pointer
• Intended to be used for the Execution of tasks in OS-based applications

Switching between Operating Modes
After reset the CR16CP starts operating in Supervisor mode.
Switching from Supervisor to User is performed by setting the U-bit in the PSR register. This can be accomplished by executing the JUSR (Jump User).

Memory Organization 

• 32-bit Address Range
• Linear Address Space of 16MB of code memory (0 to 2²⁴-1)
• Linear Address Space of 4GB of data memory (0 to 2³²-1)
• Data Addressing always byte-related (i.e., data can be addressed at byte-resolution)
• Supports Data Accesses on any Alignment
• Instructions always 16-bit word-aligned

Address Space
Memory can be logically divided into the following regions:

Note: "Data", "Far Data" and "Far2 Data" distinguish data that is addressed in different ways depending on the location within address space.

Stacks
The CR16CPlus supports three types of stacks:

Interrupt Stack

• ISP Register used as Interrupt Stack Pointer
• Interrupt stack used to save and restore the program state (PC, PSR) during exception handling
• PC and PSR are automatically pushed, by the hardware before entering an exception service procedure
• RETX instruction pops PC and PSR back from the interrupt stack

Supervisor Program Stack

• SP Register (R15) used as Supervisor Program Stack Pointer
• Used by C Compiler to pass arguments to functions
• Used by C Compiler to store local variables
• PUSH, POP and POPRET instructions adjust the SP automatically

User Program Stack

• USP Register used as User Program Stack Pointer (if PSR.U = 1)
• Used by C Compiler to pass arguments to functions
• Used by C Compiler to store local variables
• PUSH, POP and POPRET instructions adjust the SP automatically

The separate Supervisor and User Stack may save stack space in applications based on an operating system. In that case, the Supervisor stack is used as program stack for the OS kernel (running in Supervisor mode), whereas User stack is allocated for application tasks (running in User Mode).

Exception Handling 

Exception Types

• Non-Maskable Interrupt (NMI)
• Maskable Interrupts (from up to 112 Sources, managed by Interrupt Controller Unit)
• Traps
  • Supervisor (SVC)
  • Divide-by-Zero (DIZ)
  • Flag (FLG)
  • Software Breakpoint (BPT)
  • Trace (i.e. Single-Step) (TRC)
  • Undefined Instruction (UND)
  • Illegal Address (IAD)
  • Debug (DBG)
  • In-System-Emulation (ISE)

Note: The TRC, DBG and ISE traps are not used anymore, due to the addition of on-chip debug support.

Dispatch Table
The CR16CPlus uses a vectored exception scheme. Upon occurrence of an exception the CPU automatically reads out the start address of the exception service routine from a dispatch table, based on an exception-specific offset within the dispatch table (Vector Number).

In case of a maskable Interrupt the vector number is read by the CPU from a dedicated, memory-mapped register of the Interrupt Controller.

The dispatch table can be located anywhere within the available data address range. The base address of the dispatch table must be defined via the INTBASE register of the CR16CPuls.

Exception Processing

1. Save PSR and PC on Interrupt Stack (ISP)
2. Clear PSR.I bit to 0 => Interrupts disabled
3. Clear PSR.U bit to 0 => Enter Supervisor Mode
4. Read Vector Number from Interrupt Controller (if Maskable Interrupt)
5. Read ISR Start Address from Dispatch Table
6. Jump to ISR and execute.
7. ISR terminated by RETX Instruction RETX restores PSR and PC from Interrupt Stack.

(ISR = Interrupt Service Routine)

Instruction Set 

Key Features of the CR16 Instruction Set:

• High Code-density due to variable Instruction Length (2/4/6 Byte Instructions)
• Support for Integer and Q-Format (-1…+1-1LSB) Arithmetic
• Multiply-Accumulate Instructions
• Efficient Bit-Manipulation Instructions in Register and Memory
• Load/Store Instruction for Single or Multiple Registers

Addressing Modes 

Sample System Architecture 

The block diagram below shows the architecture of a sample CR16CPlus-based system.

An Instruction is cache is place between the CR16CPlus core and the system AHB in order to speed-up program execution and to reduce the overall system bus utilization of the CPU. Lower-speed peripherals and I/O devices reside on the APB and are connected to the high-speed AHB via an AHB-APB Bridge.

On-Chip Debug 

JTAG-based Debug-only (Nexus5001 Class 1 compliant)

• Min 4-pin JTAG (IEEE149.1) Communication with Tool
• Up to 16 hardware Breakpoints/Watchpoints
• Instruction Single-Step
• Non-intrusive measurement of execution time (clock cycles) between two Watchpoints
• Optional “Freeze” of Peripherals while CPU stopped in Debug Mode