Communications Infrastructure

Reference Designs (All)

• Low IF Receiver System with 16-bit 130 MSPS ADC16V130, LMK04031B, LP5900, LP3878
  • Small-signal (-20 dBFS) SNR of 78 dBFS and SFDR > 94 dBFS
  • Large-signal (-1 dBFS) SNR of 75.8 dBFS and SFDR > 84 dBFS
  • Total integrated jitter < 250 fs
• High IF Receiver System with 14-bit 155 MSPS ADC14V155, LMH6515, LMK03001C
  • Reference design performance for a 169 MHz input signal
  • Small-signal SNR of 72 dBFS and SFDR > 90 dBFS
  • Large-signal SNR 68.3 dBFS and SFDR of 77 dBFS
• Low IF Receiver System with Dual 14-bit 105 MSPS ADC14DS105, LMH6552, LMK02000
  • Reference design performance for input signals up to 40 MHz
  • Small-signal SNR of 74 dBFS and SFDR greater than 90 dBFS
  • Large-signal SNR of 73.3 dBFS and SFDR greater than 85 dBFS
• Clock Distribution on ATCA backplane - DS91D176EVK Evaluation Kit has ATCA connector and includes multiple M-LVDS transceivers. User can select stub lengths from .25 to 2 inches and trace characteristic impedance from 80 to 130 ohms.
  • AN-1503 - Designing an ATCA compliant Clock Distribution Network
• DP83640 10/100 Ethernet with IEEE 1588 PTP Support and Sub-10ns Timing

Design Information

Signal Path

• Signal-Path Designer® #111 - Selecting Amplifiers, ADCs, and Clocks for High-Performance (PDF)
• SignalPath Designer #110 Extending the Signal Path Over Data Transmission Lines (PDF)
• Signal-Path Designer® #107 Delay Calibration of Signal Path Interconnect (PDF)
• AN-1558 - Clocking High-Speed A/D Converters
• AN-1704 - High-Speed ADC Input Driver
• AN-1716 - Driving High-Speed ADCs
• AN-1718 - Diff Amp Apps Up to 400 MHz
• AN-1719 - Noise Analysis - Fully Differential Amp
• AN-1950 - Silently Powering Low-Noise Applications

Clock & Timing

• AN-1721 - High-Speed ADCs - Interfacing, Driving, and Clocking
• AN-1926 - Introduction to M-LVDS and Clock and Data Distribution Applications
• AN-1503 - Designing an ATCA Compliant M-LVDS Clock Distribution Network
• Challenges of clocking a high-definition world (Part 1 / Part 2)
• AN-1910 - LMK04000 Family Phase Noise Characterization
• AN-1879 - Designing a fractional N PLL
• AN-1173 - High-Speed Bus LVDS Clock Distribution Using the DS92CK16 Clock Distribution

Interface

• SignalPath Designer #110 Extending the Signal Path Over Data Transmission Lines (PDF)
• Signal-Path Designer® #107 Delay Calibration of Signal Path Interconnect (PDF)
• AN-1821 - CPRI Repeater System
• AN-1729 - DP83640 IEEE 1588 PTP Synchronized Clock Output
• AN-1541 - Driving Signals Over XAUI Backplanes Using DS42MB100/B200/BR400
• AN-1399 - Enabling Redundancy in Multi-Gigabit Links with DS40MB200
• AN-1398 - PCB Design Techniques for DS40MB200
• AN-1389 - Setting Pre-Emphasis Level for DS40MB200 4Gb/s Mux/Buffer
• AN-1887 - Expanding the Payload with National’s FPGA-Link

Power Management

• AN-1950 - Silently Powering Low-Noise Applications
• Buck Regulator Topologies for Wide Input/Output Voltage Differentials
• Overcoming Challenges in Designing Step Down Regulator Applications with >40V of Input Voltage
• Best Layout Practices for Switching Power Supplies
• Advanced Topics in Powering FPGAs
• Power Supply Design Considerations for Modern FPGAs
• Power Management Considerations for FPGAs and ASICs
• Power Supply Design for Power over Ethernet Applications
• Analyzing Power Modules
• Operation and Benefits of Active-Clamp Forward Power Converters
• Inside Current Mode Control
• Feedback Techniques for Crossing the Isolation Boundary
• Communications System Power Supply Designs
• Power Supply Design and the Thinking Engineer
• Comparing Topologies and the Design Rules of the Game
• Communications System Power Supply Designs
• Power Supply Design Using WEBENCH Tools
• Power Supply Design Techniques for FPGAs

System Monitoring & Reconfiguration

• Multiple Remote Diode Temperature Sensing
• Tiny Temperature Sensors for Remote Systems
• Thermal Management for High Performance Processor Systems
• AN-1262 - Four-Speed Fan Control Using Simple Remote Diode Temperature Sensor
• AN-1340 - Simplified Programming of Xilinx Devices Using a SCANSTA111/112 JTAG Chain Mux
• AN-1327 - Simplified Programming of Altera FPGA's using a SCANSTA111/112 Scan Chain Mux

• Application Notes
• Evaluation Boards
• Models & Software
• Packaging
• Reference Designs
• Solutions for Altera FPGAs
• Solutions for Xilinx FPGAs
• Technical Support
• WEBENCH Design Tools

Online Seminars (All)

• Signal Conditioning for Backplane
• Boosting FPGA and CPLD Interface Performance for off-board Data Transmission
• Bus Low Voltage Differential Signaling (BLVDS)
• Clocking and Timing
• Advantages and Pitfalls of Using Fractional N PLLs
• Local Oscillator – Characteristics and Design Considerations
• PLL Concepts
• PLL Loop Filter Optimization
• Introduction to Cascaded and Push-Pull Power Topologies
• High Voltage Switching Power Topologies and Power Management ICs
• Introduction to Emulated Current Mode (ECM) Control and the new SIMPLE SWITCHER® Buck Regulators
• Powering FPGAs: Design Considerations, IC Solutions and Tools

Signal-Path Designer Articles
Published every other month, the Signal-Path Designer newsletter's feature articles cover signal-path design techniques.

Power Designer Articles
Published bi-monthly, Power Designer's technical articles cover key power design tips and techniques for today's design engineers.

eLearning at National
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Isolated Supply Overview and Design Trade-Offs

Analog Edge App Notes
National's monthly analog design technical journal.

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Related Sites

• Data Conversion
• Amplifiers
• Clock & Timing
• Wireless (PLL/VCO)
• RF Detectors
• Interface / LVDS
• Ethernet
• Power Management
• Temperature Sensors