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Advanced PLL Concepts |
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Research Assignement Answers |
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| Q: |
What are the three different types of fractional compensation methods? |
| A: |
Delay Compensation: Since the root cause is an instantaneous phase error, it seems sensible to try to correct this with an instantaneous phase delay.
Current Compensation: A current is injected into the loop filter to try to cancel the fractional spurs.
Sigma Delta Compensation: Sigma delta noise shaping is used here. It is based on the concepts of over sampling sigma delta converters.
Refer to: "Fractional Compensation" slide in the Fractional N PLL presentation and PLL Performance, Simulation and Design, by Dean Banerjee. (pages 163-165)
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| Q: |
What performance parameters does the loop filter affect? |
| A: |
It influences switching time, loop bandwidth and reference spurs. Refer to: "Loop Filter" slide from PLL Building Blocks presentation
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| Q: |
If I keep the same comparison frequency, but double the N counter value, what is the impact on phase noise inside the loop bandwidth? |
| A: |
Phase noise will increase by 6 dB. The phase noise will increase by a factor of 10*log(N). Refer to: "Table of Transfer Functions" slide of the PLL Performance Presentation, and pg 36 of PLL Performance, Simulation and Design, by Dean Banerjee.
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| Q: |
If a 1 GHz signal and a 900 MHz signal are input to a mixer: What are the frequencies of the two intermodulation products? |
| A: |
1.1 GHz and 800 MHz. See reference: "Interdemodulation Distortion" slide of the Non-PLL RF Basics presentation |
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| Q: |
If I have a comparison frequency of 200 KHz, approximately what is the minimum loop bandwidth I can have to change from 889 - 915 MHz to a 1 KHz tolerance in less than 500 uS? |
| A: |
Answers will vary, but will be around 5.5 KHz. Refer to: WEBENCH™ EasyPLL Online Simulation Tools, to do this, set the lock time constraint to 500 uS and design for minimum spur gain. |