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PLL Performance |
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Research Assignement Answers |
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| Q: |
Define Lock time (Switching time). |
| A: |
This is defined as the time that it takes for the PLL to change from one frequency to another for a given frequency step size to within a given tolerance.
Refer to: "Switching (Lock time)" slide of the PLL Performance Presentation |
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| Q: |
If I keep the same comparison frequency, but double the N counter value, what is the impact on phase noise inside the loop bandwidth? |
| A: |
Phase noise will increase by 6 dB. The phase noise will increase by a factor of 10*log(N).
Refer to: "Table of Transfer Functions" slide of the PLL Performance Presentation, and pg 36 of PLL Performance, Simulation and Design, by Dean Banerjee. |
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| Q: |
Which of these PLLs does not have Fastlock? |
| A: |
75% reduction.
Refer to: "About the Fastlock Glitch" slide of the PLL Performance Presentation |
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