Objective: To gain an understanding of Loop Filter Design and Simulation with the use WEBENCH® EasyPLL Online Simulation Tools.
Length: 90 minutes
Published Date: Jul 30, 04
Step(s) to complete
- View online seminar
- Complete the suggested assignments
- Complete the online test to receive a certificate from Bob Pease
Online Seminar:
PLL Loop Filter Optimization
About the Presentor: Dean Banerjee, Deborah Brown, and Khang Nguyen
This seminar discusses various issues related to passive loop filter designs and presents new techniques using EasyPLL for optimizing passive loop filters for better performance.
About the Instructor: Dean Banerjee is a Senior Wireless Applications Engineer with National Semiconductor's Wireless Products division and is the author of "PLL Performance, Simulation, and Design". During this time, he has assisted in the development and support of various PLL synthesizer chips.
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Reading Assignment:
- Loop Filter Optimization
- WEBENCH® EasyPLL Online Simulation Tools help
- WIRELESS.NATIONAL.COM
Additional Resources:
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Research Assignment:
From the Loop Filter Optimization presentation (and notes) and the WEBENCH®.
EasyPLL Online Simulation Tools, please answer the following questions:
- If I have a comparison frequency of 200 KHz, approximately what is the minimum loop bandwidth I can have to change from 889 - 915 MHz to a 1 KHz tolerance in less than 500 uS?
- Suppose I have a frequency of 889-915 MHz. What N divider value do I design for and how is it calculated?
- How do I choose my loop bandwidth to design for minimum RMS phase error?
- What does National Semiconductor's WEBENCH® EasyPLL Online Simulation Tools have to offer a designer?
CHECK ALL ANSWERS HERE
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