Objective: To gain an understanding of Fractional PLLs. Including Sigma Delta Fractional PLLs, traditional Fractional PLLs, Integer PLLs and their differences. Also discusses cycle slipping, lock time, phase noise and spur levels.
Length: 90 minutes
Published Date: Jul 30, 04
Step(s) to complete
- View online seminar
- Complete the suggested assignments
- Complete the online test to receive a certificate from Bob Pease
Online Seminar:
Advantages and Pitfalls of Using Fractional N PLLs
About the Presentor: Dean Banerjee is a Senior Wireless Applications Engineer with National Semiconductor's Wireless Products division and is the author of "PLL Performance, Simulation, and Design". During this time, he has assisted in the development and support of various PLL synthesizer chips.
This seminar concentrates on performance criteria of lock time, phase noise and spur levels.
About the Instructor: Dean Banerjee is a Senior Wireless Applications Engineer with National Semiconductor's Wireless Products division and is the author of "PLL Performance, Simulation, and Design". During this time, he has assisted in the development and support of various PLL synthesizer chips.
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Reading Assignment:
Additional Resources:
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Research Assignment:
From the online seminar and reading material, please answer the following questions:
- What are the three different types of fractional compensation methods? Briefly define them.
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If the comparison frequency is 19.68 MHz and the loop bandwidth of a PLL is 10 kHz, what effect would you expect for cycle slipping to have on the lock time and why?
CHECK ALL ANSWERS HERE
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