Objective: Develop a better understanding of PLL performance. Includes phase noise, lock time and spurs.
Length: 60 minutes
Published Date: Jul 30, 04
Step(s) to complete
- Complete the suggested assignments
- Complete the online test to receive a certificate from Bob Pease
About the Instructor: Dean Banerjee is a Senior Wireless Applications Engineer with National Semiconductor's Wireless Products division and is the author of "PLL Performance, Simulation, and Design". During this time, he has assisted in the development and support of various PLL synthesizer chips.
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Reading Assignment:
Additional Resources:
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Research Assignment:
- Define Lock time (Switching time).
- If I keep the same comparison frequency, but double the N counter value, what is the impact on phase noise inside the loop bandwidth?
- Which of these PLLs does not have Fastlock?
a) LMX2306
b) LMX2310U
c) LMX2311U
d) LMX2324
CHECK ALL ANSWERS HERE
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