Overview: This seminar examines how
to enhance an FPGA's I/O signals for reliably transmitting data off-board.
An overview of FPGAs will show the families that can benefit from the I/O
enhancements. Then the seminar presents a more detailed look at six design
issues and the recommended solutions using high-performance interface devices.
Length: 60 minutes
Published Date: July 2005
Topics covered in this online seminar include:
- FPGA I/O for driving transmission line data transfers
- Interface products that enhance the transmission line performance
- Design problems where an Interface product complements FPGA
- Solutions for 6 common transmission line design problems
Presenter: Stephen Kempainen
member of the Technical Staff, Marketing Manager, Interface Division.
As a Marketing Director for the Interface Division, Kempainen is responsible
for National's high-speed LVDS, CML, and LVPECL Interface products. He
also directs technical marketing and system architecture for new products
that utilize National's industry-leading SerDes and signal conditioning
technology.
Kempainen started his career at National in 1990 as an Applications Engineer.
He also worked for more than 2 years as a Technical Editor at the prestigious
EE trade publication, EDN Magazine, where his editorial responsibilities
included Communications and Networking topics. He has had 32 articles
published in multiple trade journals and presented papers at many industry
conferences. Kempainen has been active in industry standard work. He acted
as the working group chair for the IEEE 1596.3-1996 LVDS for Scalable
Coherent Interface (SCI) industry standard.
Kempainen earned his BS degree in Electronics Engineering from San Francisco
State University.
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