Overview: The rise of fractional N PLLs,
and especially Sigma Delta Fractional PLLs brings the opportunity for significant
performance enhancements in some applications, but other applications favor
the use of integer PLLs. This presentation concentrates on performance criteria
of lock time, phase noise and spur levels.
Length: 60 minutes
Published Date: February 2003
Topics covered in this online seminar include:
- Basic Theory of Integer, Fractional N, and Sigma-Delta Fractional
N PLLs
- Lock Time and issues with cycle slipping
- Phase noise comparison of integer and fractional PLLs
- Fractional Spurs and a comparison with integer N PLL Spurs
- Competitive Analysis for Some of National's Competitor's PLLs
 Presenter:
Dean Banerjee is a Senior Wireless Applications Engineer with National
Semiconductor's Wireless Products division and is the author of "PLL
Performance, Simulation, and Design". During this time, he has assisted
in the development and support of various PLL synthesizer chips. |
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